gmicro.md

gcc-2.95.3 Linux下最常用的C编译器

;;- Machine description for GNU compiler, Fujitsu Gmicro Version
;;  Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc.
;;  Contributed by M.Yuhara, Fujitsu Laboratories LTD.

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;; Among other things, the copyright
;; notice and this notice must be preserved on all copies.


;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.


;;- instruction definitions

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;;- When naming insn's (operand 0 of define_insn) be careful about using
;;- names from other targets machine descriptions.

;;- cpp macro #define NOTICE_UPDATE_CC is essentially a no-op for the 
;;- gmicro; no compares are eliminated.

;;- The original structure of this file is m68k.md.

;; ??? Work to be done:
;; Add patterns for ACB and SCB instructions.
;; Add define_insn patterns to recognize the insns that extend a byte
;; to a word and add it into a word, etc.

;;- Some of these insn's are composites of several Gmicro op codes.
;;- The assembler (or final @@??) insures that the appropriate one is
;;- selected.

(define_insn ""
  [(set (match_operand:DF 0 "push_operand" "=m")
	(match_operand:DF 1 "general_operand" "rmfF"))]
  ""
  "*
{
  if (FPU_REG_P (operands[1]))
    return \"fmov.d %f1,%0\";
  return output_move_double (operands);
}")

(define_insn ""
  [(set (match_operand:DI 0 "push_operand" "=m")
	(match_operand:DF 1 "general_operand" "rmF"))]
  ""
  "*
{
  return output_move_double (operands);
}")

;; We don't want to allow a constant operand for test insns because
;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
;; be folded while optimizing anyway.

(define_insn "tstsi"
  [(set (cc0)
	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
  ""
  "cmp:z.w #0,%0")

(define_insn "tsthi"
  [(set (cc0)
	(match_operand:HI 0 "nonimmediate_operand" "rm"))]
  ""
  "cmp:z.h #0,%0")

(define_insn "tstqi"
  [(set (cc0)
	(match_operand:QI 0 "nonimmediate_operand" "rm"))]
  ""
  "cmp:z.b #0,%0")
  

(define_insn "tstsf"
  [(set (cc0)
	(match_operand:SF 0 "general_operand" "fmF"))]
  "TARGET_FPU"
  "*
{
  cc_status.flags = CC_IN_FPU;
  return \"ftst.s %0\";
}")


(define_insn "tstdf"
  [(set (cc0)
	(match_operand:DF 0 "general_operand" "fmF"))]
  "TARGET_FPU"
  "*
{
  cc_status.flags = CC_IN_FPU;
  return \"ftst.d %0\";
}")

;; compare instructions.

;; (operand0 - operand1)
(define_insn "cmpsi"
  [(set (cc0)
	(compare (match_operand:SI 0 "nonimmediate_operand" "ri,rm")
		 (match_operand:SI 1 "general_operand" "rm,rmi")))]
  ""
  "*
{
  int signed_flag = my_signed_comp (insn);

  if (which_alternative == 0)
    {
      cc_status.flags |= CC_REVERSED;
      if (signed_flag && GET_CODE (operands[0]) == CONST_INT)
	{
	  register rtx xfoo;
	  xfoo = operands[1];
	  operands[0] = operands[1];
	  operands[1] = xfoo;
	  return cmp_imm_word (INTVAL (operands[1]), operands[0]);
	}
      if (signed_flag)
	return \"cmp.w %0,%1\"; 
      return \"cmpu.w %0,%1\"; 
    }
  if (signed_flag)
    {
      if (GET_CODE (operands[1]) == CONST_INT)
	return cmp_imm_word (INTVAL (operands[1]), operands[0]);
      return \"cmp.w %1,%0\"; 
    }
  else
    return \"cmpu.w %1,%0\"; 
}")

(define_insn "cmphi"
  [(set (cc0)
	(compare (match_operand:HI 0 "nonimmediate_operand" "ri,rm")
		 (match_operand:HI 1 "general_operand" "rm,rmi")))]
  ""
  "*
{
  int signed_flag = my_signed_comp (insn);

  if (which_alternative == 0)
    {
      cc_status.flags |= CC_REVERSED;
      if (signed_flag)
	return \"cmp.h %0,%1\"; 
      return \"cmpu.h %0,%1\"; 
    }
  if (signed_flag)
    return \"cmp.h %1,%0\"; 
  return \"cmpu.h %1,%0\"; 
}")

(define_insn "cmpqi"
  [(set (cc0)
	(compare (match_operand:QI 0 "nonimmediate_operand" "ri,rm")
		 (match_operand:QI 1 "general_operand" "rm,rmi")))]
  ""
  "*
{
  int signed_flag = my_signed_comp (insn);

  if (which_alternative == 0)
    {
      cc_status.flags |= CC_REVERSED;
      if (signed_flag)
	return \"cmp.b %0,%1\"; 
      return \"cmpu.b %0,%1\"; 
    }
  if (signed_flag)
    return \"cmp.b %1,%0\"; 
  return \"cmpu.b %1,%0\"; 
}")


(define_insn "cmpdf"
  [(set (cc0)
	(compare (match_operand:DF 0 "general_operand" "f,mG")
		 (match_operand:DF 1 "general_operand" "fmG,f")))]
  "TARGET_FPU"
  "*
{
  cc_status.flags = CC_IN_FPU;

  if (FPU_REG_P (operands[0]))
    return \"fcmp.d %f1,%f0\";
  cc_status.flags |= CC_REVERSED;
  return \"fcmp.d %f0,%f1\";
}")


(define_insn "cmpsf"
  [(set (cc0)
	(compare (match_operand:SF 0 "general_operand" "f,mG")
		 (match_operand:SF 1 "general_operand" "fmG,f")))]
  "TARGET_FPU"
  "*
{
  cc_status.flags = CC_IN_FPU;
  if (FPU_REG_P (operands[0]))
    return \"fcmp.s %f1,%0\";
  cc_status.flags |= CC_REVERSED;
  return \"fcmp.s %f0,%1\";
}")

;; Recognizers for btst instructions.

(define_insn ""
  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
			    (const_int 1)
			    (match_operand:SI 1 "general_operand" "rmi")))]
  ""
  "btst %1.w,%0.b")

(define_insn ""
  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "rm")
			    (const_int 1)
			    (match_operand:SI 1 "general_operand" "rmi")))]
  ""
  "btst %1.w,%0.w")

;; The following two patterns are like the previous two
;; except that they use the fact that bit-number operands (offset)
;; are automatically masked to 3 or 5 bits when the base is a register.

(define_insn ""
  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
			    (const_int 1)
			    (and:SI
			       (match_operand:SI 1 "general_operand" "rmi")
			       (const_int 7))))]
  ""
  "btst %1.w,%0.b")

(define_insn ""
  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
			    (const_int 1)
			    (and:SI
			       (match_operand:SI 1 "general_operand" "rmi")
			       (const_int 31))))]
  ""
  "btst %1.w,%0.w")

; More various size-patterns are allowed for btst, but not
; included yet.  M.Yuhara


(define_insn ""
  [(set (cc0) (and:SI (sign_extend:SI
		       (sign_extend:HI
			(match_operand:QI 0 "nonimmediate_operand" "rm")))
		      (match_operand:SI 1 "general_operand" "i")))]
  "(GET_CODE (operands[1]) == CONST_INT
    && (unsigned) INTVAL (operands[1]) < 0x100
    && exact_log2 (INTVAL (operands[1])) >= 0)"
  "*
{
  register int log = exact_log2 (INTVAL (operands[1]));
  operands[1] = GEN_INT (log);
  return \"btst %1,%0.b\";
}")

; I can add more patterns like above. But not yet.  M.Yuhara


; mtst is supported only by G/300.

(define_insn ""
  [(set (cc0) 
	(and:SI (match_operand:SI 0 "general_operand" "%rmi")
		(match_operand:SI 1 "general_operand" "rm")))]
  "TARGET_G300"
  "*
{
  if (GET_CODE (operands[0]) == CONST_INT)
    return \"mtst.w %0,%1\";
  return \"mtst.w %1,%0\";
}")

(define_insn ""
  [(set (cc0) 
	(and:HI (match_operand:HI 0 "general_operand" "%rmi")
		(match_operand:HI 1 "general_operand" "rm")))]
  "TARGET_G300"
  "*
{
  if (GET_CODE (operands[0]) == CONST_INT)
    return \"mtst.h %0,%1\";
  return \"mtst.h %1,%0\";
}")

(define_insn ""
  [(set (cc0) 
	(and:QI (match_operand:QI 0 "general_operand" "%rmi")
		(match_operand:QI 1 "general_operand" "rm")))]
  "TARGET_G300"
  "*
{
  if (GET_CODE (operands[0]) == CONST_INT)
    return \"mtst.b %0,%1\";
  return \"mtst.b %1,%0\";
}")



;; move instructions

/* added by M.Yuhara */
;; 1.35.04 89.08.28 modification start
;; register_operand -> general_operand
;; ashift -> mult 

(define_insn ""
  [(set (mem:SI (plus:SI
		  (match_operand:SI 0 "general_operand" "r")
		  (ashift:SI
		      (match_operand:SI 1 "general_operand" "r")
		      (const_int 2))))
	(match_operand:SI 2 "general_operand" "rmi"))]
  ""
  "*
{
  return \"mov.w %2,@(%0:b,%1*4)\";
}")

(define_insn ""
  [(set (mem:SI (plus:SI
		  (ashift:SI
		      (match_operand:SI 0 "general_operand" "r")
		      (const_int 2))
		  (match_operand:SI 1 "general_operand" "r")))
	(match_operand:SI 2 "general_operand" "rmi"))]
  ""
  "*
{
  return \"mov.w %2,@(%1:b,%0*4)\";
}")


(define_insn ""
  [(set (mem:SI (plus:SI
		  (match_operand:SI 0 "register_operand" "r")
		  (mult:SI
		      (match_operand:SI 1 "register_operand" "r")
		      (const_int 4))))
	(match_operand:SI 2 "general_operand" "rmi"))]
  ""
  "*
{
  return \"mov.w %2,@(%0:b,%1*4)\";
}")

(define_insn ""
  [(set (mem:SI (plus:SI
		  (mult:SI
		      (match_operand:SI 0 "register_operand" "r")
		      (const_int 4))
		  (match_operand:SI 1 "register_operand" "r")))
	(match_operand:SI 2 "general_operand" "rmi"))]
  ""
  "*
{
  return \"mov.w %2,@(%1:b,%0*4)\";
}")


(define_insn ""
  [(set (mem:SI (plus:SI
		  (match_operand:SI 0 "general_operand" "r")
		  (plus:SI
		      (match_operand:SI 1 "register_operand" "r")
		      (match_operand:SI 2 "register_operand" "i"))))
	(match_operand:SI 3 "general_operand" "rmi"))]
  ""
  "*
{
  return \"mov.w %3,@(%c2,%0,%1)\";
}")

(define_insn ""
  [(set (mem:SI (plus:SI
		  (plus:SI
		      (match_operand:SI 0 "register_operand" "r")
		      (match_operand:SI 1 "register_operand" "r"))
		  (match_operand:SI 2 "general_operand" "i")))
	(match_operand:SI 3 "general_operand" "rmi"))]
  ""
  "*
{
  return \"mov.w %3,@(%c2,%0,%1)\";
}")


(define_insn ""
  [(set (mem:SI (plus:SI
		  (match_operand:SI 0 "general_operand" "i")
		  (plus:SI
		      (match_operand:SI 1 "register_operand" "r")
		      (mult:SI
			  (match_operand:SI 2 "register_operand" "r")
			  (const_int 4)))))
	(match_operand:SI 3 "general_operand" "rmi"))]
  ""
  "*
{
  return \"mov.w %3,@(%1:b,%0,%2*4)\";
}")

;; 89.08.28 1.35.04 modification end

;; Should add "!" to op2 ??

;; General move-address-to-operand should handle these.
;; If that does not work, please figure out why.

;(define_insn ""
;  [(set (match_operand:SI 0 "push_operand" "=m")
;	(plus:SI
;	    (match_operand:SI 1 "immediate_operand" "i")
;	    (match_operand:SI 2 "general_operand" "r")))]
;  ""
;  "mova.w @(%c1,%2),%-")

;(define_insn ""
;  [(set (match_operand:SI 0 "push_operand" "=m")
;	(plus:SI
;	    (match_operand:SI 1 "general_operand" "r")
;	    (match_operand:SI 2 "immediate_operand" "i")))]
;  ""
;  "mova.w @(%c2,%1),%-")


(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=m")
	(minus:SI
	    (match_operand:SI 1 "general_operand" "r")
	    (match_operand:SI 2 "immediate_operand" "i")))]
  ""
  "mova.w @(%n2,%1),%-")



;; General case of fullword move.

(define_insn "movsi"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(match_operand:SI 1 "general_operand" "rmi"))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == CONST_INT)
    return mov_imm_word (INTVAL (operands[1]), operands[0]);
  /* if (address_operand (operands[1], SImode))
     return \"mova.w %1,%0\"; */
  if (push_operand (operands[0], SImode))
    return \"mov.w %1,%-\";
  return \"mov.w %1,%0\";
}")

/* pushsi 89.08.10 for test M.Yuhara */
/*
(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=m")
	(match_operand:SI 1 "general_operand" "rmi"))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == CONST_INT)
    return mov_imm_word (INTVAL (operands[1]), operands[0]);
  if (push_operand (operands[0], SImode))
    return \"mov.w %1,%-\";
  return \"mov.w %1,%0\";
}")
*/


(define_insn "movhi"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(match_operand:HI 1 "general_operand" "rmi"))]
  ""
  "*
{
  if (push_operand (operands[0], SImode))
    return \"mov.h %1,%-\";
  return \"mov.h %1,%0\";
}")

;; Is the operand constraint "+" necessary ????
;; Should I check push_operand ????

(define_insn "movstricthi"
  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
	(match_operand:HI 1 "general_operand" "rmi"))]
  ""
  "mov.h %1,%0");

(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(match_operand:QI 1 "general_operand" "rmi"))]
  ""