we32k.md

gcc-2.95.3 Linux下最常用的C编译器

;; Machine description for GNU compiler, AT&T we32000 Version
;; Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
;; Contributed by John Wehle ([e-mail])

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 1, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.


;;- instruction definitions

;;- @@The original PO technology requires these to be ordered by speed,
;;- @@    so that assigner will pick the fastest.

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;;- When naming insn's (operand 0 of define_insn) be careful about using
;;- names from other targets machine descriptions.

;; move instructions

(define_insn ""
  [(set (match_operand:DF 0 "push_operand" "=m")
        (match_operand:DF 1 "general_operand" "mrF"))]
  ""
  "*
  {
  output_push_double(&operands[1]);

  return \"\";
  }")

(define_insn "movdf"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=mr")
        (match_operand:DF 1 "general_operand" "mrF"))]
  ""
  "*
  {
  output_move_double(operands);

  return \"\";
  }")

(define_insn ""
  [(set (match_operand:SF 0 "push_operand" "=m")
        (match_operand:SF 1 "general_operand" "mrF"))]
  ""
  "pushw %1")

(define_insn "movsf"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=mr")
        (match_operand:SF 1 "general_operand" "mrF"))]
  ""
  "movw %1, %0")

(define_insn ""
  [(set (match_operand:DI 0 "push_operand" "=m")
        (match_operand:DI 1 "general_operand" "mriF"))]
  ""
  "*
  {
  output_push_double(&operands[1]);

  return \"\";
  }")

(define_insn "movdi"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=mr")
        (match_operand:DI 1 "general_operand" "mriF"))]
  ""
  "*
  {
  output_move_double(operands);

  return \"\";
  }")

(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=m")
        (match_operand:SI 1 "general_operand" "mri"))]
  ""
  "pushw %1")

(define_insn "movsi"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (match_operand:SI 1 "general_operand" "mri"))]
  ""
  "movw %1, %0")

(define_insn "movhi"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
        (match_operand:HI 1 "general_operand" "mri"))]
  ""
  "movh %1, %0")

(define_insn "movqi"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
        (match_operand:QI 1 "general_operand" "mri"))]
  ""
  "movb %1, %0")

;; add instructions

(define_insn ""
  [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
        (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
                 (match_operand:DI 2 "general_operand" "oriF")))]
  ""
  "*
  {
  rtx label[1];
  rtx lsw_operands[3];

  if (GET_CODE (operands[0]) == REG)
    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
  else
    if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
      lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
    else
      abort();

  if (GET_CODE (operands[2]) == REG)
    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
  else
    if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
      lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
    else
      if (GET_CODE (operands[2]) == CONST_DOUBLE)
        {
        lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
        operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
        }
      else
        if (GET_CODE (operands[2]) == CONST_INT)
          {
          lsw_operands[2] = operands[2];
          operands[2] = const0_rtx;
          }
        else
          abort();

  label[0] = gen_label_rtx();
  LABEL_NUSES(label[0]) = 1;

  output_asm_insn(\"addw2 %2, %0\", operands);
  output_asm_insn(\"addw2 %2, %0\", lsw_operands);
  output_asm_insn(\"BCCB %l0\", label);
  output_asm_insn(\"INCW %0\", operands);
  output_asm_insn(\"%l0:\", label);

  return \"\";
  }")

(define_insn "adddi3"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
        (plus:DI (match_operand:DI 1 "general_operand" "oriF")
                 (match_operand:DI 2 "general_operand" "oriF")))]
  ""
  "*
  {
  rtx label[1];
  rtx lsw_operands[3];

  if (GET_CODE (operands[0]) == REG)
    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
  else
    if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
      lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
    else
      abort();

  if (GET_CODE (operands[1]) == REG)
    lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
  else
    if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
      lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
    else
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
        {
        lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH(operands[1]));
        operands[1] = GEN_INT (CONST_DOUBLE_LOW(operands[1]));
        }
      else
        if (GET_CODE (operands[1]) == CONST_INT)
          {
          lsw_operands[1] = operands[1];
          operands[1] = const0_rtx;
          }
        else
          abort();

  if (GET_CODE (operands[2]) == REG)
    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
  else
    if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
      lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
    else
      if (GET_CODE (operands[2]) == CONST_DOUBLE)
        {
        lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
        operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
        }
      else
        if (GET_CODE (operands[2]) == CONST_INT)
          {
          lsw_operands[2] = operands[2];
          operands[2] = const0_rtx;
          }
        else
          abort();

  label[0] = gen_label_rtx();
  LABEL_NUSES(label[0]) = 1;

  output_asm_insn(\"addw3 %2, %1, %0\", operands);
  output_asm_insn(\"addw3 %2, %1, %0\", lsw_operands);
  output_asm_insn(\"BCCB %l0\", label);
  output_asm_insn(\"INCW %0\", operands);
  output_asm_insn(\"%l0:\", label);

  return \"\";
  }")

(define_insn ""
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
                 (match_operand:SI 2 "general_operand" "mri")))]
  ""
  "addw2 %2, %0")

(define_insn "addsi3"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
        (plus:SI (match_operand:SI 1 "general_operand" "mri")
                 (match_operand:SI 2 "general_operand" "mri")))]
  ""
  "addw3 %2, %1, %0")

(define_insn ""
  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
        (plus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
                 (match_operand:HI 2 "general_operand" "mri")))]
  ""
  "addh2 %2, %0")

(define_insn "addhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
        (plus:HI (match_operand:HI 1 "general_operand" "mri")
                 (match_operand:HI 2 "general_operand" "mri")))]
  ""
  "addh3 %2, %1, %0")

(define_insn ""
  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
        (plus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
                 (match_operand:QI 2 "general_operand" "mri")))]
  ""
  "addb2 %2, %0")

(define_insn "addqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
        (plus:QI (match_operand:QI 1 "general_operand" "mri")
                 (match_operand:QI 2 "general_operand" "mri")))]
  ""
  "addb3 %2, %1, %0")

;; subtract instructions

(define_insn ""
  [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
        (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
                 (match_operand:DI 2 "general_operand" "oriF")))]
  ""
  "*
  {
  rtx label[1];
  rtx lsw_operands[3];

  if (GET_CODE (operands[0]) == REG)
    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
  else
    if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
      lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
    else
      abort();

  if (GET_CODE (operands[2]) == REG)
    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
  else
    if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
      lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
    else
      if (GET_CODE (operands[2]) == CONST_DOUBLE)
        {
        lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
        operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
        }
      else
        if (GET_CODE (operands[2]) == CONST_INT)
          {
          lsw_operands[2] = operands[2];
          operands[2] = const0_rtx;
          }
        else
          abort();

  label[0] = gen_label_rtx();
  LABEL_NUSES(label[0]) = 1;

  output_asm_insn(\"subw2 %2, %0\", operands);
  output_asm_insn(\"subw2 %2, %0\", lsw_operands);
  output_asm_insn(\"BCCB %l0\", label);
  output_asm_insn(\"DECW %0\", operands);
  output_asm_insn(\"%l0:\", label);

  return \"\";
  }")

(define_insn "subdi3"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
        (minus:DI (match_operand:DI 1 "general_operand" "oriF")
                 (match_operand:DI 2 "general_operand" "oriF")))]
  ""
  "*
  {
  rtx label[1];
  rtx lsw_operands[3];

  if (GET_CODE (operands[0]) == REG)
    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
  else
    if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
      lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
    else
      abort();

  if (GET_CODE (operands[1]) == REG)
    lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
  else
    if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
      lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
    else
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
        {
        lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH(operands[1]));
        operands[1] = GEN_INT (CONST_DOUBLE_LOW(operands[1]));
        }
      else
        if (GET_CODE (operands[1]) == CONST_INT)
          {
          lsw_operands[1] = operands[1];
          operands[1] = const0_rtx;
          }
        else
          abort();

  if (GET_CODE (operands[2]) == REG)
    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
  else
    if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
      lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
    else
      if (GET_CODE (operands[2]) == CONST_DOUBLE)
        {
        lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
        operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
        }
      else
        if (GET_CODE (operands[2]) == CONST_INT)
          {
          lsw_operands[2] = operands[2];
          operands[2] = const0_rtx;
          }
        else
          abort();

  label[0] = gen_label_rtx();
  LABEL_NUSES(label[0]) = 1;

  output_asm_insn(\"subw3 %2, %1, %0\", operands);
  output_asm_insn(\"subw3 %2, %1, %0\", lsw_operands);
  output_asm_insn(\"BCCB %l0\", label);
  output_asm_insn(\"DECW %0\", operands);
  output_asm_insn(\"%l0:\", label);