ns32k.md

gcc-2.95.3 Linux下最常用的C编译器

  split_di (operands, 3, low, high);
  xops[0] = low[0];
  xops[1] = high[0];
  xops[2] = low[2];
  xops[3] = high[2];

  if (GET_CODE (xops[2]) == CONST_INT)
    {
      int i = INTVAL (xops[2]);

      if (i <= 7 && i >= -8) 
        {
          if (i == 0)
	    {
	      i = INTVAL (xops[3]);
	      if (i <= 7 && i >= -8)
                output_asm_insn (\"addqd %3,%1\", xops);
	      else
                output_asm_insn (\"addd %3,%1\", xops);
	    }
	  else
	    {
              output_asm_insn (\"addqd %2,%0\", xops);
              output_asm_insn (\"addcd %3,%1\", xops);
	    }
	  return \"\";
	}
    }
  output_asm_insn (\"addd %2,%0\", xops);
  output_asm_insn (\"addcd %3,%1\", xops);
  return \"\";
}")

;; See Note 1
(define_insn "addsi3"
  [(set (match_operand:SI 0 "general_operand" "=g,=g&<")
	(plus:SI (match_operand:SI 1 "general_operand" "%0,r")
		 (match_operand:SI 2 "general_operand" "g,i")))]
  ""
  "*
{
  if (which_alternative == 1)
    {
      if (GET_CODE (operands[2]) == CONST_INT)
        {
	  int i = INTVAL (operands[2]);
	  if (NS32K_DISPLACEMENT_P (i))
	    return \"addr %c2(%1),%0\";
	  else
	    return \"movd %1,%0\;addd %2,%0\";
        }
      else
        {
          if (flag_pic) 
            return \"addr %a2[%1:b],%0\";
	  else
	    return \"addr %c2(%1),%0\";
        }
    }
  else if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      if (i <= 7 && i >= -8)
	return \"addqd %2,%0\";
      else if (! TARGET_32532 && GET_CODE (operands[0]) == REG
	       && NS32K_DISPLACEMENT_P (i))
	return \"addr %c2(%0),%0\";
    }
  return \"addd %2,%0\";
}")

(define_insn "addhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(plus:HI (match_operand:HI 1 "general_operand" "%0")
		 (match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);
      if (i <= 7 && i >= -8)
	return \"addqw %2,%0\";
    }
  return \"addw %2,%0\";
}")

(define_insn ""
  [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
	(plus:HI (match_operand:HI 1 "general_operand" "0")
		 (match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == CONST_INT
      && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
    return \"addqw %2,%0\";
  return \"addw %2,%0\";
}")

(define_insn "addqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(plus:QI (match_operand:QI 1 "general_operand" "%0")
		 (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);
      if (i <= 7 && i >= -8)
	return \"addqb %2,%0\";
    }
  return \"addb %2,%0\";
}")

(define_insn ""
  [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
	(plus:QI (match_operand:QI 1 "general_operand" "0")
		 (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == CONST_INT
      && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
    return \"addqb %2,%0\";
  return \"addb %2,%0\";
}")

;;- All kinds of subtract instructions.

(define_insn "subdf3"
  [(set (match_operand:DF 0 "general_operand" "=lm")
	(minus:DF (match_operand:DF 1 "general_operand" "0")
		  (match_operand:DF 2 "general_operand" "lmF")))]
  "TARGET_32081"
  "subl %2,%0")

(define_insn "subsf3"
  [(set (match_operand:SF 0 "general_operand" "=fm")
	(minus:SF (match_operand:SF 1 "general_operand" "0")
		  (match_operand:SF 2 "general_operand" "fmF")))]
  "TARGET_32081"
  "subf %2,%0")

(define_insn ""
  [(set (reg:SI 25)
	(minus:SI (reg:SI 25)
		  (match_operand:SI 0 "immediate_operand" "i")))]
  "GET_CODE (operands[0]) == CONST_INT"
  "*
{
  if (! TARGET_32532 && GET_CODE(operands[0]) == CONST_INT 
      && INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
    return \"adjspb %0\";
  return \"adjspd %0\";
}")

(define_insn "subdi3"
  [(set (match_operand:DI 0 "general_operand" "=ro")
	(minus:DI (match_operand:DI 1 "general_operand" "0")
		  (match_operand:DI 2 "general_operand" "ron")))]
  ""
  "*
{
  rtx low[3], high[3], xops[4];
  split_di (operands, 3, low, high);
  xops[0] = low[0];
  xops[1] = high[0];
  xops[2] = low[2];
  xops[3] = high[2];

  if (GET_CODE (xops[2]) == CONST_INT)
    {
      int i = INTVAL (xops[2]);

      if (i <= 8 && i >= -7)
        {
          if (i == 0)
	    {
	      i = INTVAL (xops[3]);
	      if (i <= 8 && i >= -7)
                output_asm_insn (\"addqd %n3,%1\", xops);
	      else
                output_asm_insn (\"subd %3,%1\", xops);
	    }
	  else
	    {
              output_asm_insn (\"addqd %n2,%0\", xops);
              output_asm_insn (\"subcd %3,%1\", xops);
	    }
	  return \"\";
	}
    }
  output_asm_insn (\"subd %2,%0\", xops);
  output_asm_insn (\"subcd %3,%1\", xops);
  return \"\";
}")

(define_insn "subsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(minus:SI (match_operand:SI 1 "general_operand" "0")
		  (match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      if (i <= 8 && i >= -7)
        return \"addqd %n2,%0\";
    }
  return \"subd %2,%0\";
}")

(define_insn "subhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(minus:HI (match_operand:HI 1 "general_operand" "0")
		  (match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      if (i <= 8 && i >= -7)
        return \"addqw %n2,%0\";
    }
  return \"subw %2,%0\";
}")

(define_insn ""
  [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
	(minus:HI (match_operand:HI 1 "general_operand" "0")
		  (match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == CONST_INT
      && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
    return \"addqw %n2,%0\";
  return \"subw %2,%0\";
}")

(define_insn "subqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(minus:QI (match_operand:QI 1 "general_operand" "0")
		  (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      if (i <= 8 && i >= -7)
	return \"addqb %n2,%0\";
    }
  return \"subb %2,%0\";
}")

(define_insn ""
  [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
	(minus:QI (match_operand:QI 1 "general_operand" "0")
		  (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == CONST_INT
      && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
    return \"addqb %n2,%0\";
  return \"subb %2,%0\";
}")

;;- Multiply instructions.

(define_insn "muldf3"
  [(set (match_operand:DF 0 "general_operand" "=lm")
	(mult:DF (match_operand:DF 1 "general_operand" "%0")
		 (match_operand:DF 2 "general_operand" "lmF")))]
  "TARGET_32081"
  "mull %2,%0")

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "general_operand" "=fm")
	(mult:SF (match_operand:SF 1 "general_operand" "%0")
		 (match_operand:SF 2 "general_operand" "fmF")))]
  "TARGET_32081"
  "mulf %2,%0")

;; See note 1
(define_insn "mulsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(mult:SI (match_operand:SI 1 "general_operand" "%0")
		 (match_operand:SI 2 "general_operand" "g")))]
  ""
  "muld %2,%0")

(define_insn "mulhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(mult:HI (match_operand:HI 1 "general_operand" "%0")
		 (match_operand:HI 2 "general_operand" "g")))]
  ""
  "mulw %2,%0")

(define_insn "mulqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(mult:QI (match_operand:QI 1 "general_operand" "%0")
		 (match_operand:QI 2 "general_operand" "g")))]
  ""
  "mulb %2,%0")

(define_insn "umulsidi3"
  [(set (match_operand:DI 0 "general_operand" "=g")
	(mult:DI (zero_extend:DI
		  (match_operand:SI 1 "nonimmediate_operand" "0"))
		 (zero_extend:DI
		  (match_operand:SI 2 "nonimmediate_operand" "g"))))]
  ""
  "meid %2,%0")

;; divmod insns: We can only do the unsigned case.
(define_expand "udivmodsi4"
  [(parallel
  [(set (match_operand:SI 0 "reg_or_mem_operand" "")
	(udiv:SI (match_operand:SI 1 "general_operand" "")
		     (match_operand:SI 2 "general_operand" "")))
   (set (match_operand:SI 3 "reg_or_mem_operand" "")
	(umod:SI (match_dup 1) (match_dup 2)))])]
  ""
  "
{
  rtx temp = gen_reg_rtx(DImode);
  rtx insn, first, last;
  first = emit_move_insn(gen_lowpart(SImode, temp), operands[1]);
  emit_move_insn(gen_highpart(SImode, temp), const0_rtx);
  emit_insn(gen_udivmoddisi4_internal(temp, temp, operands[2]));
  last = emit_move_insn(temp, temp);
  {
    rtx divdi, moddi, divsi, modsi;
    divsi = gen_rtx (UDIV, SImode, operands[1], operands[2]);
    modsi = gen_rtx (UMOD, SImode, operands[1], operands[2]);
    divdi = gen_rtx (ZERO_EXTEND, DImode, divsi);
    moddi = gen_rtx (ZERO_EXTEND, DImode, modsi);
    REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
			         REG_NOTES (first));
    REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
                                gen_rtx (EXPR_LIST, REG_EQUAL,
                       gen_rtx (IOR, DImode, moddi,
                               gen_rtx (ASHIFT, DImode, divdi, GEN_INT(32))),
                       REG_NOTES (last)));
  }

  insn = emit_move_insn(operands[0], gen_highpart(SImode, temp));
  insn = emit_move_insn(operands[3], gen_lowpart(SImode, temp));
  DONE;
}")

;; If we try and describe what this does, we have to zero-expand an
;; operand, which prevents it being a constant (VOIDmode) (see udivmoddisi4
;; below. This udivmoddisi4_internal never matches anything and is only
;; ever used when explicitly emitted by a define_expand.
(define_insn "udivmoddisi4_internal"
  [(set (match_operand:DI 0 "reg_or_mem_operand" "=rm")
        (unspec:DI [(match_operand:DI 1 "reg_or_mem_operand" "0")
                    (match_operand:SI 2 "general_operand" "g")] 0))]
  ""
  "deid %2,%0")

;; Retain this insn which *does* have a pattern indicating what it does,
;; just in case the compiler is smart enough to recognize a substitution.
(define_insn "udivmoddisi4"
  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=rm") 1)
	(truncate:SI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
		 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "g")))))
   (set (subreg:SI (match_operand:DI 3 "register_operand" "=0") 0)
	(truncate:SI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
  ""
  "deid %2,%0")

;; Part word variants. These seem to never be used at the moment (gcc
;; 2.7.2.2). The code generation prefers to zero extend hi's and qi's
;; and use signed div and mod. Keep these insns incase that changes.
;; divmod should have an advantage when both div and mod are needed. However,
;; divmod uses two registers, so maybe the compiler knows best.

(define_expand "udivmodhi4"
  [(parallel
  [(set (match_operand:HI 0 "reg_or_mem_operand" "")
	(udiv:HI (match_operand:HI 1 "general_operand" "")
		     (match_operand:HI 2 "general_operand" "")))
   (set (match_operand:HI 3 "reg_or_mem_operand" "")
	(umod:HI (match_dup 1) (match_dup 2)))])]
  ""
  "
{
  rtx temp = gen_reg_rtx(DImode);
  rtx insn, first, last;
  first = emit_move_insn(gen_lowpart(HImode, temp), operands[1]);
  emit_move_insn(gen_highpart (HImode, temp), const0_rtx);
  operands[2] = force_reg(HImode, operands[2]);
  emit_insn(gen_udivmoddihi4_internal(temp, temp, operands[2]));
  last = emit_move_insn(temp, temp);
  {
    rtx divdi, moddi, divhi, modhi;
    divhi = gen_rtx (UDIV, HImode, operands[1], operands[2]);
    modhi = gen_rtx (UMOD, HImode, operands[1], operands[2]);
    divdi = gen_rtx (ZERO_EXTEND, DImode, divhi);
    moddi = gen_rtx (ZERO_EXTEND, DImode, modhi);
    REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
			         REG_NOTES (first));
    REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
                                gen_rtx (EXPR_LIST, REG_EQUAL,
                       gen_rtx(IOR, DImode, moddi,
                               gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
                       REG_NOTES (last)));
  }

  insn = emit_move_insn(operands[0], gen_highpart(HImode, temp));
  insn = emit_move_insn(operands[3], gen_lowpart(HImode, temp));
  DONE;
}")

;; deiw wants two hi's in seperate registers or else they can be adjacent
;; in memory. DI mode will ensure two registers are available, but if we
;; want to allow memory as an operand we would need SI mode. There is no
;; way to do this, so just restrict operand 0 and 1 to be in registers.
(define_insn "udivmoddihi4_internal"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (unspec:DI [(match_operand:DI 1 "register_operand" "0")
                    (match_operand:HI 2 "general_operand" "g")] 0))]
  ""
  "deiw %2,%0")

(define_insn "udivmoddihi4"
  [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 1)
	(truncate:HI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
		 (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "g")))))
   (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
	(truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
  ""
  "deiw %2,%0")

(define_expand "udivmodqi4"
  [(parallel
  [(set (match_operand:QI 0 "reg_or_mem_operand" "")
	(udiv:QI (match_operand:QI 1 "general_operand" "")
		     (match_operand:QI 2 "general_operand" "")))
   (set (match_operand:QI 3 "reg_or_mem_operand" "")
	(umod:QI (match_dup 1) (match_dup 2)))])]
  ""
  "
{
  rtx temp = gen_reg_rtx(DImode);
  rtx insn, first, last;
  first = emit_move_insn(gen_lowpart(QImode, temp), operands[1]);
  emit_move_insn(gen_highpart(QImode, temp), const0_rtx);
  operands[2] = force_reg(QImode, operands[2]);
  emit_insn(gen_udivmoddiqi4_internal(temp, temp, operands[2]));
  last = emit_move_insn(temp, temp);