📄 qt2chgr_inc.asm
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Motorola Semiconductors (H.K.) Ltd.
* 8/16 bit MCU - Application
*
* FileName : QT2CHGR_INC.asm
* Title : Include file for One Lithium Ion Cell Charger Reference Code
* MCU : MC68HC908QT2
* Assembler : P&E Microcomputer Systems - CASM08Z (v3.16)
*
* Author : Roger Fan
*
* DD/MM/YY Rev. Modified comments.
* History : 19/12/02 1.0 Initial release
* 04/03/03 1.1 Correct the cycle time from 0.8us to 0.3125us for
* all time delay routines (20ms and 500ms)
*
*
* NOTE: TCH0 IS USED AS PWM FUNCTION, NOT VREF NEED. THIS CHARGER NEED 1% VDD AS REFERENCE.
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Disclaimer of All Warranties & Liabilities :-
* This Program is a freeware to demonstrate the operation of HC08 micro-
* controller. In no event will Motorola be liable for any damages, or any
* incidental or consequential damages arising out of the use of or
* inability to use this program. User agrees that Motorola does not make
* any warranties of any kind that the program does not or will not
* infringe any copyright, patent, trade secret or other intellectual
* property right of any third party in any country.
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*********************************************************************
* Config TIMER module as UNBuffered PWM for channel 0 *
*********************************************************************
Init_TIM:
MOV #$30,TSC ; stop and reset the TIM counter, disable TOF interrupt
MOV #$1A,TSC0 ; prescaler, set up channel 0 for unbuffered PWM
;mov #%01010000,TSC0 ; ch0 interrupt enable, TCH0 use as port function output Low
MOV #$00,TCH0H ; output low at TCH0
MOV #$00,TCH0L
;MOV #$01,TMODH ; set period (PWM Period); 12.5KHz for fbus=3.2MHz
;MOV #$00,TMODL
MOV #$00,TMODH ; set period (PWM Period); 25KHz for fbus=3.2MHz
MOV #$80,TMODL
BCLR 5,TSC ; clear TSTOP, enable timer counter,
; timer counter start only when charger is in ready to charge state
LDA TSC0 ; read TCH0 status and control register to clear CH0F flag
bclr CH0F,TSC0 ; clear CH0F flag
lda TSC ; clear TOF flag
bclr TOF,TSC
rts
;********************************************************************
; Subroutine AD_Check
; Check AD in and do average, AD channel config store in Temp_Buff before subroutine call
;VARIABLE : BufferL, BufferH, ADC_COUNT ,adc_cnt0
; state(diff bit),
;********************************************************************
AD_Check
STA Temp_Buff ; temp_buf
CLR BufferL ; l_buf
CLR BufferH ;
MOV #!4,ADC_COUNT ;
Ad_chk0
lda Temp_Buff
sta adscr
Ad_chk1
BRCLR COCO,ADSCR,*
LDA ADR
;------------------------------------------------------------
; adr x 4 -----> /4 ; average of 4 data
;------------------------------------------------------------
avr_cal
add BufferL
bcc avr_cal0 ; if carry, increas BufferH
inc BufferH
avr_cal0
sta BufferL
dbnz ADC_COUNT,ad_chk0 ; wait until 4 samples got.
lda BufferH
lsra
ror BufferL
lsra
ror BufferL
sta BufferH
lda BufferL
rts
***********************************************************************
check_tim_out ; every tick = 4.24288s
brclr timer_tick,FLAG,exit_CTO
bclr timer_tick,FLAG ; clear the timer_tick flag
dbnz chrg_tim_cnt_L,exit_CTO
dbnz chrg_tim_cnt_H,exit_CTO
bset time_overflow,FLAG
bclr TOIE,TSC ; time out, disable TOF interrupt
exit_CTO
rts
***********************************************************************
***********************************************************************
*
* Date : 03-DEC-02
* Title : Routines for 500ms delay (should be 200ms)
* Note : - Flash LED, For 12.8MHz ICG 68HC908QT2
* - Bus clock = 12.8MHz/4 = 3.2MHz
* - 1 cycle = 1/3.2MHz = 0.3125us
* 200ms = 62.5K~ = 250
* ((2560+2+3)*250+2+3)*0.3125us = 200.4ms
***********************************************************************
DLY_500ms
LDX #$FA ; [2]
; ldx #$7C ; delay 100ms
DLY_500ms_X
LDA #$FF ; [2]
DLY_500ms_A
sta $FFFF ; [4] clear COP
nop ; [1]
nop ; [1]
nop ; [1]
dbnza DLY_500ms_A ; [3] ;10*256=2560~
dbnzx DLY_500ms_X ; [3]
rts ; [3]
***********************************************************************
*
* Date : 03-DEC-02
* Title : Routines for 20ms delay
* Note : - For 12.8MHz ICG 68HC908QT2
* - Bus clock = 12.8MHz/4 = 3.2MHz
* - 1 cycle = 0.3125us
*
* ((2560+2+3)*25+2+3)*0.3125us = 20.0ms
***********************************************************************
DLY_20ms
LDX #25 ; [2]
DLY_20ms_X
LDA #$FF ; [2]
DLY_20ms_A
sta $FFFF ; [4] clear COP
nop ; [1]
nop ; [1]
nop ; [1]
dbnza DLY_20ms_A ; [3] ;10*256=2560~
dbnzx DLY_20ms_X ; [3]
rts ; [3]
***********************************************************************
*
* Date : 23-FEB-99
* Title : Routines to Tx byte out of s/w emulated RS232 serial output
* Note : - For 12.8MHz ICG 68HC908QT2, RS232C works at 19200,n,8,1
* - Bus clock = 12.8MHz/4 = 3.2MHz, PTA3 is used as the serial o/p
* - Modified from Tony Luk's HC05 source
*
***********************************************************************
* ====== Subroutines =====================================================
* ORG ROM_BEG
* [DEBUG] ------------------------------------------------------------- *
* DSRL_OUT - Tx Byte out of TSDta line(RS232: 19200,n,8,1) *
* In : V_IRbyte transmit byte *
* Out : <nil> *
* Call : DLY_BIT
* |__|-|_|-|_|-|_|-|_|---- bit 0 tx first
* st 1 0 1 0 1 0 1 0 stop $55 *
* --------------------------------------------------------------------- *
DSRL_OUT:
sei ; disable interrupts to ensure
; correct bit frame timing
bset b_TSDta,DDR_CTRL ; config PTA3 output
sta COPCTL ; clear cop
*
* --- Force "Start" Bit --------------------------------------------------
bclr b_TSDta,Port_CTRL ; force low TSDta line
bsr DLY_BIT ; delay 1 bit frame [4 clk]
*
* --- Force B0-7 Data Bits -----------------------------------------------
lda V_IRbyte ; load Tx byte [3 clk]
lda V_IRbyte ; <dummy> [3 clk]
ldx #8 ; 8 data bits [2 clk]
DSOT_NEXT: ; 26 clk ?
rora ; shift Tx bit to C-bit [1 clk] ? LSB tx first for RS232
;rola ; MSB tx first for Oscillate scope
bcs DSOT_BHIGH ; C-bit set ? [3 clk] ?
DSOT_BLOW: ; ?
bclr b_TSDta,Port_CTRL ; force low TSDta line [4 clk] ?
bra DSOT_BCTI ; [3 clk] ?
DSOT_BHIGH: ; ?
bset b_TSDta,Port_CTRL ; force high TSDta line [4 clk] ?
bra DSOT_BCTI ; [3 clk] ?
DSOT_BCTI: ; ?
bsr DLY_BIT ; delay 1 bit frame [4 clk] ?
decx ; next data bit [1 clk] ?
bne DSOT_NEXT ; ~last data bit ? [3 clk] ?
*
* --- Force "Stop" Bit ---------------------------------------------------
bset b_TSDta,Port_CTRL ; force high TSDta line
bsr DLY_BIT ; delay 1 bit frame [4 clk]
*
* ------------------------------------------------------------------------
DSOT_EXIT:
cli ; enable interrupts
bsr DLY_BIT ; delay 1 bit frame [4 clk]
sta copctl
bsr DLY_BIT ; delay 1 bit frame [4 clk]
* (ensure packet separation)
; bclr b_TSDta,DDR_CTRL ; config PTA3 backto input
cli
rts
* [DEBUG] ------------------------------------------------------------- *
* DLY_BIT - delay 1 bit frame(for 19200 bps) *
* In : <nil> *
* Out : <nil> *
* Call : <nil> *
* Note :- For (Fosc = 12.8 MHz) and (baud rate = 19200 bps) *
* 1 bit frame = ((12.8e6 / 4) / 19200) *
* = 166.7 CPU clocks *
* --------------------------------------------------------------------- *
* (assume overhead from calling routine = [15 clk]
* bsr NC_DLY_BIT [4 clk]
* 15+3+2+1+6*23+3+4=307
DLY_BIT:
stx V_DlyX ; store <reg_X> [3 clk]
ldx #$17 ; #23 [2 clk]
tstx ; <dummy> [1 clk]
DBIT_NEXT:
tstx ; <dummy> [1 clk]
tstx ; <dummy> [1 clk]
decx ; [1 clk]
bne DBIT_NEXT ; [3 clk]
*
ldx V_DlyX ; load <reg_X> [3 clk]
*
* ------------------------------------------------------------------------
DBIT_EXIT:
rts ; [4 clk]
* [DEBUG] ------------------------------------------------------------- *
* HEX_T_CHAR - convert hex digit to ASCII char *
* In : reg_A hex digit *
* Out : reg_A ASCII char *
* Call : <nil> *
* Note :- content of reg_X is corrupted *
* --------------------------------------------------------------------- *
HEX_T_CHAR:
tax
lda TABLE_HEX_CHAR,x
rts
*
* ------------------------------------------------------------------------
*
* Lookup Table to convert Hex Digit --> ASCII Char
* -------------------------------------------------
TABLE_HEX_CHAR:
db '0','1','2','3','4','5','6','7'
db '8','9','A','B','C','D','E','F'
ADCDELAY PSHX
LDX #$ff
stx COUNT
DAGAIN DECX
dec COUNT
BNE DAGAIN
PULX
RTS
*************************************************************************
* *
* Tx data T, V, I. *
* *
*************************************************************************
Tx_data brclr rs232_tick,FLAG1,exit_Tx_data
bclr rs232_tick,FLAG1
mov #$19,ms500_cnt ; 500ms
Tx_full
lda CURRENT
sta V_IRbyte
jsr DSRL_out ; transmit the data out
JSR ADCDELAY
lda VOLTAGE
sta V_IRbyte
jsr DSRL_out ; transmit the data out
JSR ADCDELAY
lda TEMPERATURE
sta V_IRbyte
jsr DSRL_out ; transmit the data out
JSR ADCDELAY
exit_Tx_data
rts
*************************************************************************
* *
* LED Display Routine *
* *
*************************************************************************
Flashing_RED_LED
BCLR RED_LED,PTB
JSR DLY_500ms
BSET RED_LED,PTB
bra Flashing_RED_LED
rts
*
* delay 152ms
*
delay ldx #$F9 ; [2] $F9 =250d
delayX lda #$F9 ; [2]
sta $FFFF ; [4] clear COP
delayA decA
bne delayA ; [3]
decX
bne delayX ; [3]
rts ; [4]
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