mc68hc908qt4.equ

freescale充电器原程序,可直接编译

; bit position masks
mCOPRS:      equ    %10000000     ;COP reset period selection
mLVISTOP:    equ    %01000000     ;LVI enable in stop mode
mLVIRSTD:    equ    %00100000     ;LVI reset disable
mLVIPWRD:    equ    %00010000     ;LVI power disable
mLVI5OR3:    equ    %00001000     ;LVI 5V or 3V operating mode
mSSREC:      equ    %00000100     ;Short stop recovery
mSTOP:       equ    %00000010     ;STOP instruction enable
mCOPD:       equ    %00000001     ;COP disable

;****  Timer Interface module (TIM)  ****************************************************
;*
TSC:         equ    $20           ;Timer status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
TOF:         equ    7             ;TIM overflow flag
TOIE:        equ    6             ;TIM overflow interrupt enable
TSTOP:       equ    5             ;TIM Stop bit
TRST:        equ    4             ;TIM Reset bit
PS2:         equ    2             ;Prescaler select bit 2
PS1:         equ    1             ;Prescaler select bit 1
PS0:         equ    0             ;Prescaler select bit 0
; bit position masks
mTOF:        equ    %10000000     ;TIM overflow flag
mTOIE:       equ    %01000000     ;TIM overflow interrupt enable
mTSTOP:      equ    %00100000     ;TIM Stop bit
mTRST:       equ    %00010000     ;TIM Reset bit
mPS2:        equ    %00000100     ;Prescaler select bit 2
mPS1:        equ    %00000010     ;Prescaler select bit 1
mPS0:        equ    %00000001     ;Prescaler select bit 0

TSC0:        equ    $25           ;Timer channel 0 status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CH0F:        equ    7             ;Channel 0 flag
CH0IE:       equ    6             ;Channel 0 interrupt enable
MS0B:        equ    5             ;Mode select bit B
MS0A:        equ    4             ;Mode select bit A
ELS0B:       equ    3             ;Edge/level select bit B
ELS0A:       equ    2             ;Edge/level select bit A
TOV0         equ    1             ;Toggle on overflow
CH0MAX       equ    0             ;Channel 0 maximum duty cycle
; bit position masks
mCH0F:       equ    %10000000     ;Channel 0 flag
mCH0IE:      equ    %01000000     ;Channel 0 interrupt enable
mMS0B:       equ    %00100000     ;Mode select bit B
mMS0A:       equ    %00010000     ;Mode select bit A
mELS0B:      equ    %00001000     ;Edge/level select bit B
mELS0A:      equ    %00000100     ;Edge/level select bit A
mTOV0        equ    %00000010     ;Toggle on overflow
mCH0MAX      equ    %00000001     ;Channel 0 maximum duty cycle

TSC1:       equ    $28           ;Timer channel 1 status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
CH1F:        equ    7             ;Channel 1 flag
CH1IE:       equ    6             ;Channel 1 interrupt enable
MS1B:        equ    5             ;Mode select bit B
MS1A:        equ    4             ;Mode select bit A
ELS1B:       equ    3             ;Edge/level select bit B
ELS1A:       equ    2             ;Edge/level select bit A
TOV1         equ    1             ;Toggle on overflow
CH1MAX       equ    0             ;Channel 1 maximum duty cycle
; bit position masks
mCH1F:       equ    %10000000     ;Channel 1 flag
mCH1IE:      equ    %01000000     ;Channel 1 interrupt enable
mMS1B:       equ    %00100000     ;Mode select bit B
mMS1A:       equ    %00010000     ;Mode select bit A
mELS1B:      equ    %00001000     ;Edge/level select bit B
mELS1A:      equ    %00000100     ;Edge/level select bit A
mTOV1        equ    %00000010     ;Toggle on overflow
mCH1MAX      equ    %00000001     ;Channel 1 maximum duty cycle

TCNTH:       equ    $21           ;Timer counter register high
TCNTL:       equ    $22           ;Timer counter register Low
TMODH:       equ    $23           ;Timer counter modulo register high
TMODL:       equ    $24           ;Timer counter modulo register low
TCH0H:       equ    $26           ;Timer channel 0 register high
TCH0L:       equ    $27           ;Timer channel 0 register low
TCH1H:       equ    $29           ;Timer channel 1 register high
TCH1L:       equ    $2A           ;Timer channel 1 register low

;****  Oscillator Module (OSC)  ***************************************************
;*
OSCSTAT:     equ    $36           ;Oscillator status register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
ECGON:       equ    1             ;External clock generator on
ECGST:       equ    0             ;External clock status
; bit position masks
mECGON:      equ    %00000010     ;External clock generator on
mECGST:      equ    %00000001     ;External clock status

OSCTRIM:     equ    $38           ;Oscillator trim register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
TRIM7:       equ    7             ;Internal oscillator trim factor bit 7
TRIM6:       equ    6             ;Internal oscillator trim factor bit 6
TRIM5:       equ    5             ;Internal oscillator trim factor bit 5
TRIM4:       equ    4             ;Internal oscillator trim factor bit 4
TRIM3:       equ    3             ;Internal oscillator trim factor bit 3
TRIM2:       equ    2             ;Internal oscillator trim factor bit 2
TRIM1:       equ    1             ;Internal oscillator trim factor bit 1
TRIM0:       equ    0             ;Internal oscillator trim factor bit 0
; bit position masks
mTRIM7:      equ    %10000000     ;Internal oscillator trim factor bit 7
mTRIM6:      equ    %01000000     ;Internal oscillator trim factor bit 6
mTRIM5:      equ    %00100000     ;Internal oscillator trim factor bit 5
mTRIM4:      equ    %00010000     ;Internal oscillator trim factor bit 4
mTRIM3:      equ    %00001000     ;Internal oscillator trim factor bit 3
mTRIM2:      equ    %00000100     ;Internal oscillator trim factor bit 2
mTRIM1:      equ    %00000010     ;Internal oscillator trim factor bit 1
mTRIM0:      equ    %00000001     ;Internal oscillator trim factor bit 0

TRIMLOC:     equ    $FFC0         ;Internal oscillator trim value


;****  Analog-to-Digital Converter (ADC)  ***********************************************
;*
ADSCR:       equ    $3C           ;ADC status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
COCO:        equ    7             ;Conversions complete
AIEN:        equ    6             ;ADC interrupt enable bit
ADCO:        equ    5             ;ADC continuous conversion
CH4:         equ    4             ;ADC channel select bit 4
CH3:         equ    3             ;ADC channel select bit 3
CH2:         equ    2             ;ADC channel select bit 2
CH1:         equ    1             ;ADC channel select bit 1
CH0:         equ    0             ;ADC channel select bit 0
; bit position masks
mCOCO:       equ    %10000000     ;Conversions complete
mAIEN:       equ    %01000000     ;ADC interrupt enable bit
mADCO:       equ    %00100000     ;ADC continuous conversion
mCH4:        equ    %00010000     ;ADC channel select bit 4
mCH3:        equ    %00001000     ;ADC channel select bit 3
mCH2:        equ    %00000100     ;ADC channel select bit 2
mCH1:        equ    %00000010     ;ADC channel select bit 1
mCH0:        equ    %00000001     ;ADC channel select bit 0

ADR:         equ    $3E           ;ADC data register

ADICLK:      equ    $3F           ;ADC input clock register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
ADIV2:       equ    7             ;ADC clock prescaler bit 2
ADIV1:       equ    6             ;ADC clock prescaler bit 1
ADIV0:       equ    5             ;ADC clock prescaler bit 0
; bit position masks
mADIV2:      equ    %10000000     ;ADC clock prescaler bit 2
mADIV1:      equ    %01000000     ;ADC clock prescaler bit 1
mADIV0:      equ    %00100000     ;ADC clock prescaler bit 0

;****  System Integration Module (SIM)  *************************************************
;*
BSR:        equ    $FE00          ;SIM break status register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
SBSW        equ    1              ;SIM break stop/wait
; bit position masks
mSBSW:      equ    %00000010      ;SIM break stop/wait

SRSR:       equ    $FE01          ;SIM reset status register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
POR:        equ    7              ;Power-on reset
PIN:        equ    6              ;External reset
COP:        equ    5              ;COP reset
ILOP:       equ    4              ;Illegal opcode reset
ILAD:       equ    3              ;Illegal address reset
MODRST:     equ    2              ;Monitor mode entry module reset
LVI:        equ    1              ;LVI reset
; bit position masks
mPOR:       equ    %10000000     ;Power-on reset
mPIN:       equ    %01000000     ;External reset
mCOP:       equ    %00100000     ;COP reset
mILOP:      equ    %00010000     ;Illegal opcode reset
mILAD:      equ    %00001000     ;Illegal address reset
mMODRST:    equ    %00000100     ;Monitor mode entry module reset
mLVI:       equ    %00000010     ;LVI reset

BRKAR:      equ    $FE02         ;Break auxiliary register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
BDCOP:      equ    0             ;Break disable COP
; bit position masks
mBDCOP:     equ    %00000001     ;Break disable COP

BFCR:       equ    $FE03         ;Break flag control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
BCFE:       equ    7             ;Break clear flag enable
; bit position masks
mBCFE:      equ    %10000000     ;Break clear flag enable

INT1:       equ    $FE04         ;Interrupt status register 1
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
IF5:        equ    6             ;Interrupt flag 5
IF4:        equ    5             ;Interrupt flag 4
IF3:        equ    4             ;Interrupt flag 3
IF1:        equ    2             ;Interrupt flag 1

INT2:       equ    $FE05         ;Interrupt status register 2
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
IF14:       equ    7             ;Interrupt flag 14

INT3:       equ    $FE06         ;Interrupt status register 3
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
IF15:       equ    0             ;Interrupt flag 15

;****  Flash Memory  ********************************************************************
;*
FLCR:       equ    $FE08         ;Flash control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
HVEN:       equ    3             ;High-voltage enable bit mask
MASS:       equ    2             ;Mass erase control bit mask
ERASE:      equ    1             ;Erase control bit mask
PGM:        equ    0             ;Program control bit mask
; bit position masks
mHVEN:      equ    %00001000     ;High-voltage enable bit mask
mMASS:      equ    %00000100     ;Mass erase control bit mask
mERASE:     equ    %00000010     ;Erase control bit mask
mPGM:       equ    %00000001     ;Program control bit mask

FLBPR:      equ    $FFBE         ;Flash block protect register

;****  Breakpoint Module (BRK)  *********************************************************
;*
BRKH:       equ    $FE09         ;Break address register high
BRKL:       equ    $FE0A         ;Break address register low

BRKSCR:     equ    $FE0B         ;Break status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
BRKE:       equ    7             ;Break enable
BRKA:       equ    6             ;Break active
; bit position masks
mBRKE:      equ    %10000000     ;Break enable
mBRKA:      equ    %01000000     ;Break active

;****  Low-Voltage Inhibit (LVI)  *******************************************************
;*
LVISR:      equ    $FE0C         ;LVI status register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
LVIOUT:     equ    7             ;LVI output bit
; bit position masks
mLVIOUT:    equ    %10000000     ;LVI output bit

;****  Computer Operating Properly (COP)  ***********************************************
;*
COPCTL:     equ    $FFFF         ;COP control register