mc68hc908qt4.equ

freescale充电器原程序,可直接编译

;****************************************************************************************
;* Title: HC908QY4.equ                                   Copyright (c) Motorola 2002
;****************************************************************************************
;* Author:  Kazue Kikuchi
;*
;* Description:  Register and bit name definitions for MC68HC908QY4 and MC68HC908QT4
;*
;* Documentation:  MC68HC908QT4/D  Advance Information
;* Include Files:  none
;*
;* Assembler:  P&E Microcomputer Systems - CASM08Z  (v3.16)
;*
;* Revision History:
;* Rev #      Date       Who     Comments
;* ------  -----------   ------  -----------------------------------------------------
;* ES 1.0   29-Apr-02    KK      Initial release
;* ES 1.1   07-Jun-02    KK      Fixed OSCTRIM address and typos
;* ES 1.2   05-Aug-02    JS      Fixed typo in pullup register
;*
;****************************************************************************************
;****************************************************************************************
;*
;*   Motorola reserves the right to make changes without further notice to any product
;*   herein to improve reliability, function, or design.  Motorola does not assume any
;*   liability arising out of the application or use of any product, circuit, or software
;*   described herein; neither does it convey any license under its patent rights nor the
;*   rights of others.  Motorola products are not designed, intended, or authorized for
;*   use as components in systems intended for surgical implant into the body, or other
;*   applications intended to support life, or for any other application in which the
;*   failure of the Motorola product could create a situation where personal injury or
;*   death may occur.  Should Buyer purchase or use Motorola products for any such
;*   intended or unauthorized application, Buyer shall indemnify and hold Motorola and
;*   its officers, employees, subsidiaries, affiliates, and distributors harmless against
;*   all claims, costs, damages, and expenses, and reasonable attorney fees arising out
;*   of, directly or indirectly, any claim of personal injury or death associated with
;*   such unintended or unauthorized use, even if such claim alleges that Motorola was
;*   negligent regarding the design or manufacture of the part.
;*
;*   Motorola and the Motorola logo are registered trademarks of Motorola, Inc.
;****************************************************************************************

;****  Memory Map and Interrupt Vectors  ************************************************
;*
RamStart:    equ    $0080         ;Start of RAM
RamLast:     equ    $00FF         ;Last RAM location
FlashStart:  equ    $EE00         ;Start of Flash
FlashLast:   equ    $FDFF         ;Last Flash location
;
Vadc:        equ    $FFDE         ;ADC vector
Vkbd:        equ    $FFE0         ;Keyboard vector
Vtimov:      equ    $FFF2         ;Timer overflow vector
Vtimch1:     equ    $FFF4         ;Timer channel 1 vector
Vtimch0:     equ    $FFF6         ;Timer channel 0 vector
Virq:        equ    $FFFA         ;IRQ vector
Vswi:        equ    $FFFC         ;SWI vector
Vreset:      equ    $FFFE         ;Reset vector

;****  Input/Output (I/O) Ports  *******************************************************
;*
PTA:         equ    $00           ;Port A data register
; bit numbers for use in BLCR, BSET, BRCLR, and BRSET
AWUL         equ    6             ;Auto wake-up latch data
PTA5:        equ    5             ;Port A data bit 5
PTA4:        equ    4             ;Port A data bit 4
PTA3:        equ    3             ;Port A data bit 3
PTA2:        equ    2             ;Port A data bit 2
PTA1:        equ    1             ;Port A data bit 1
PTA0:        equ    0             ;Port A data bit 0
; bit position masks
mAWUL:       equ    %01000000     ;Auto wake-up latch data
mPTA5:       equ    %00100000     ;Port A data bit 5
mPTA4:       equ    %00010000     ;Port A data bit 4
mPTA3:       equ    %00001000     ;Port A data bit 3
mPTA2:       equ    %00000100     ;Port A data bit 2
mPTA1:       equ    %00000010     ;Port A data bit 1
mPTA0:       equ    %00000001     ;Port A data bit 0

PTB:         equ    $01           ;Port B data register
; bit numbers for use in BLCR, BSET, BRCLR, and BRSET
PTB7:        equ    7             ;Port B data bit 7
PTB6:        equ    6             ;Port B data bit 6
PTB5:        equ    5             ;Port B data bit 5
PTB4:        equ    4             ;Port B data bit 4
PTB3:        equ    3             ;Port B data bit 3
PTB2:        equ    2             ;Port B data bit 2
PTB1:        equ    1             ;Port B data bit 1
PTB0:        equ    0             ;Port B data bit 0
; bit position masks
mPTB7:       equ    %10000000     ;Port B data bit 7
mPTB6:       equ    %01000000     ;Port B data bit 6
mPTB5:       equ    %00100000     ;Port B data bit 5
mPTB4:       equ    %00010000     ;Port B data bit 4
mPTB3:       equ    %00001000     ;Port B data bit 3
mPTB2:       equ    %00000100     ;Port B data bit 2
mPTB1:       equ    %00000010     ;Port B data bit 1
mPTB0:       equ    %00000001     ;Port B data bit 0

DDRA:        equ    $04           ;Port A data direction register
; bit numbers for use in BLCR, BSET, BRCLR, and BRSET
DDRA5:       equ    5             ;Port A data direction bit 5
DDRA4:       equ    4             ;Port A data direction bit 4
DDRA3:       equ    3             ;Port A data direction bit 3
DDRA1:       equ    1             ;Port A data direction bit 1
DDRA0:       equ    0             ;Port A data direction bit 0
; bit position masks
mDDRA5:      equ    %00100000     ;Port A data direction bit 5
mDDRA4:      equ    %00010000     ;Port A data direction bit 4
mDDRA3:      equ    %00001000     ;Port A data direction bit 3
mDDRA1:      equ    %00000010     ;Port A data direction bit 1
mDDRA0:      equ    %00000001     ;Port A data direction bit 0

DDRB:        equ    $05           ;Port B data direction register
; bit numbers for use in BLCR, BSET, BRCLR, and BRSET
DDRB7:       equ    7             ;Port B data direction bit 7
DDRB6:       equ    6             ;Port B data direction bit 6
DDRB5:       equ    5             ;Port B data direction bit 5
DDRB4:       equ    4             ;Port B data direction bit 4
DDRB3:       equ    3             ;Port B data direction bit 3
DDRB2:       equ    2             ;Port B data direction bit 2
DDRB1:       equ    1             ;Port B data direction bit 1
DDRB0:       equ    0             ;Port B data direction bit 0
; bit position masks
mDDRB7:      equ    %10000000     ;Port B data direction bit 7
mDDRB6:      equ    %01000000     ;Port B data direction bit 6
mDDRB5:      equ    %00100000     ;Port B data direction bit 5
mDDRB4:      equ    %00010000     ;Port B data direction bit 4
mDDRB3:      equ    %00001000     ;Port B data direction bit 3
mDDRB2:      equ    %00000100     ;Port B data direction bit 2
mDDRB1:      equ    %00000010     ;Port B data direction bit 1
mDDRB0:      equ    %00000001     ;Port B data direction bit 0

PTAPUE:      equ    $0B           ;Port A input pullup enable register
; bit numbers for use in BLCR, BSET, BRCLR, and BRSET
OSC2EN:      equ    7             ;OSC2 pin enable
PTAPUE5:     equ    5             ;Port A input pull up enable bit 5
PTAPUE4:     equ    4             ;Port A input pull up enable bit 4
PTAPUE3:     equ    3             ;Port A input pull up enable bit 3
PTAPUE2:     equ    2             ;Port A input pull up enable bit 2
PTAPUE1:     equ    1             ;Port A input pull up enable bit 1
PTAPUE0:     equ    0             ;Port A input pull up enable bit 0
; bit position masks
mOSC2EN:     equ    %10000000     ;OSC2 pin enable
mPTAPUE5:    equ    %00100000     ;Port A input pull up enable bit 5
mPTAPUE4:    equ    %00010000     ;Port A input pull up enable bit 4
mPTAPUE3:    equ    %00001000     ;Port A input pull up enable bit 3
mPTAPUE2:    equ    %00000100     ;Port A input pull up enable bit 2
mPTAPUE1:    equ    %00000010     ;Port A input pull up enable bit 1
mPTAPUE0:    equ    %00000001     ;Port A input pull up enable bit 0

PTBPUE:      equ    $0C           ;Port B input pullup enable register
; bit numbers for use in BLCR, BSET, BRCLR, and BRSET
PTBPUE7:     equ    7             ;Port B input pull up enable bit 7
PTBPUE6:     equ    6             ;Port B input pull up enable bit 6
PTBPUE5:     equ    5             ;Port B input pull up enable bit 5
PTBPUE4:     equ    4             ;Port B input pull up enable bit 4
PTBPUE3:     equ    3             ;Port B input pull up enable bit 3
PTBPUE2:     equ    2             ;Port B input pull up enable bit 2
PTBPUE1:     equ    1             ;Port B input pull up enable bit 1
PTBPUE0:     equ    0             ;Port B input pull up enable bit 0
; bit position masks
mPTBPUE7:    equ    %10000000     ;Port B input pull up enable bit 7
mPTBPUE6:    equ    %01000000     ;Port B input pull up enable bit 6
mPTBPUE5:    equ    %00100000     ;Port B input pull up enable bit 5
mPTBPUE4:    equ    %00010000     ;Port B input pull up enable bit 4
mPTBPUE3:    equ    %00001000     ;Port B input pull up enable bit 3
mPTBPUE2:    equ    %00000100     ;Port B input pull up enable bit 2
mPTBPUE1:    equ    %00000010     ;Port B input pull up enable bit 1
mPTBPUE0:    equ    %00000001     ;Port B input pull up enable bit 0

;****  Keyboard Interrupt Module (KBI)  *************************************************
;*
KBSCR:       equ    $1A           ;Keyboard status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
KEYF:        equ    3             ;Keyboard flag
ACKK:        equ    2             ;Keyboard acknowledge
IMASKK:      equ    1             ;Keyboard interrupt mask
MODEK:       equ    0             ;Keyboard triggering sesitivity
; bit position masks
mKEYF:       equ    %00001000     ;Keyboard flag
mACKK:       equ    %00000100     ;Keyboard acknowledge
mIMASKK:     equ    %00000010     ;Keyboard interrupt mask
mMODEK:      equ    %00000001     ;Keyboard triggering sesitivity

KBIER:       equ    $1B           ;Keyboard interrupt enable register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
AWUIE:       equ    6             ;Auto wake-up interrupt enable
KBIE5:       equ    5             ;Port A keyboard interrupt enable bit 5
KBIE4:       equ    4             ;Port A keyboard interrupt enable bit 4
KBIE3:       equ    3             ;Port A keyboard interrupt enable bit 3
KBIE2:       equ    2             ;Port A keyboard interrupt enable bit 2
KBIE1:       equ    1             ;Port A keyboard interrupt enable bit 1
KBIE0:       equ    0             ;Port A keyboard interrupt enable bit 0
; bit position masks
mAWUIE       equ    %01000000     ;Auto wake-up interrupt enable
mKBIE5:      equ    %00100000     ;Port A keyboard interrupt enable bit 5
mKBIE4:      equ    %00010000     ;Port A keyboard interrupt enable bit 4
mKBIE3:      equ    %00001000     ;Port A keyboard interrupt enable bit 3
mKBIE2:      equ    %00000100     ;Port A keyboard interrupt enable bit 2
mKBIE1:      equ    %00000010     ;Port A keyboard interrupt enable bit 1
mKBIE0:      equ    %00000001     ;Port A keyboard interrupt enable bit 0

;****  External Interrupt (IRQ)  ********************************************************
;*
INTSCR:      equ    $1D           ;IRQ status and control register
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
IRQF1:       equ    3             ;IRQ flag
ACK1:        equ    2             ;IRQ interrupt request acknowledge
IMASK1:      equ    1             ;IRQ interrupt mask
MODE1:       equ    0             ;IRQ edge/level select
; bit position masks
mIRQF1:      equ    %00001000     ;IRQ flag
mACK1:       equ    %00000100     ;IRQ interrupt request acknowledge
mIMASK1:     equ    %00000010     ;IRQ interrupt mask
mMODE1:      equ    %00000001     ;IRQ edge/level select

;**** Configuration Registers (CONFIG)  *************************************************
;*
CONFIG2:     equ    $1E           ;Configuration register 2
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
IRQPUD:      equ    7             ;IRQ pin pullup control
IRQEN:       equ    6             ;IRQ pin function selection
OSCOPT1:     equ    4             ;Selection bit 1 for oscillator option
OSCOPT0:     equ    3             ;Selection bit 0 for oscillator option
RSTEN:       equ    0             ;RST pin function selection
; bit position masks
mIRQPUD:     equ    %10000000     ;IRQ pin pullup control
mIRQEN:      equ    %01000000     ;IRQ pin function selection
mOSCOPT1:    equ    %00010000     ;Selection bit 1 for oscillator option
mOSCOPT0:    equ    %00001000     ;Selection bit 0 for oscillator option
mRSTEN:      equ    %00000001     ;RST pin function selection

CONFIG1:     equ    $1F           ;Configuration register 1
; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
COPRS:       equ    7             ;COP reset period selection
LVISTOP:     equ    6             ;LVI enable in stop mode
LVIRSTD:     equ    5             ;LVI reset disable
LVIPWRD:     equ    4             ;LVI power disable
LVI5OR3:     equ    3             ;LVI 5V or 3V operating mode
SSREC:       equ    2             ;Short stop recovery
STOP:        equ    1             ;STOP instruction enable
COPD:        equ    0             ;COP disable