displaytb.v

一些vhdl的常用程序

`timescale 10ns/1ns

module DisplayTB;
	reg Reset,Clk128Hz;
	reg [1:0] HourH;
	reg [2:0] MinH,SecH;
	reg [3:0] HourL,MinL,SecL;
	reg HourSet,MinSet,Flash;
	wire [5:0] Drive;
	wire [6:0] Sink;
	wire AlmOut;


Display Display2(
	/*input*/.Reset(Reset),.Clk128Hz(Clk128Hz),.HourH(HourH),.HourL(HourL),.MinH(MinH),.MinL(MinL),.SecH(SecH),
	.SecL(SecL),.HourSet(HourSet),.MinSet(MinSet),.Flash(Flash),
	/*inout*/
	/*output*/.Drive(Drive),.Sink(Sink),.AlmOut(AlmOut));
	
always 
begin
	#5 Clk128Hz = 1'b0;
	#5 Clk128Hz = 1'b1;
end

always 
begin
	#640 Flash = 1'b0;
	#640 Flash = 1'b1;
end

initial
begin
	Reset = 1'b1;
	HourH = 2'h0;
	HourL = 4'h6;
	MinH = 3'h2;
	MinL = 4'h8;
	SecH = 3'h4;
	SecL = 4'h9;
	HourSet = 1'b0;
	MinSet = 1'b0;
	
	#31 Reset = 1'b0;
	#1000
	HourH = 2'h1;
	HourL = 4'h7;
	MinH = 3'h3;
	MinL = 4'h9;
	SecH = 3'h5;
	SecL = 4'h9;
	#1000 HourSet = 1'b1;
	
	#5000
	
	$stop;
	
end

endmodule