startup.s

Assembly example with RealView MDK The Assembly example shows how to create a pure assembly program

;/*****************************************************************************/
;/* STARTUP.S: Startup file for Measure Example                               */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>>                          */ 
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools.                   */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved.               */
;/* This software may only be used under the terms of a valid, current,       */
;/* end user licence from KEIL for a compatible version of KEIL software      */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/


; *** Startup Code (executed after Reset) ***


; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F

I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled


; Internal RAM Address
RAM_Base        EQU     0x00000000      ; after Ramap
RAM_Base_Boot   EQU     0x00300000      ; after Reset until Remap 


;// <h> Stack Configuration (Stack Sizes in Bytes)
;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
;// </h>

UND_Stack_Size  EQU     0x00000000
SVC_Stack_Size  EQU     0x00000000
ABT_Stack_Size  EQU     0x00000000
FIQ_Stack_Size  EQU     0x00000000
IRQ_Stack_Size  EQU     0x00000040
USR_Stack_Size  EQU     0x00000200

Stack_Size      EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                         FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size

Stack_Top       EQU     Stack_Mem + Stack_Size


;// <h> Heap Configuration
;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>

Heap_Size       EQU     0x00000000

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem        SPACE   Heap_Size


;// <h> External Bus Interface (EBI)
EBI_BASE        EQU     0xFFE00000

;//   <e.13> Enable Chip Select 0 (CSR0)
;//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
;//                <i> Start Address for Chip Select Signal
;//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
;//                                      <2=> 16M Bytes  <3=> 64M Bytes
;//                <i> Selects Active Bits in Base Address
;//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
;//     <o.12>     BAT: Byte Access Type <0=> Byte-write
;//                                      <1=> Byte-select
;//     <e.5>      WSE: Enable Wait State Generation
;//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
;//     </e>
;//     <o.9..11>  TDF: Data Float Output Time <0-7>
;//                <i> Number of Cycles Added after the Transfer
;//   </e>
EBI_CSR0_Val    EQU     0x010024A9

;//   <e.13> Enable Chip Select 1 (CSR1)
;//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
;//                <i> Start Address for Chip Select Signal
;//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
;//                                      <2=> 16M Bytes  <3=> 64M Bytes
;//                <i> Selects Active Bits in Base Address
;//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
;//     <o.12>     BAT: Byte Access Type <0=> Byte-write
;//                                      <1=> Byte-select
;//     <e.5>      WSE: Enable Wait State Generation
;//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
;//     </e>
;//     <o.9..11>  TDF: Data Float Output Time <0-7>
;//                <i> Number of Cycles Added after the Transfer
;//   </e>
EBI_CSR1_Val    EQU     0x040034A5

;//   <e.13> Enable Chip Select 2 (CSR2)
;//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
;//                <i> Start Address for Chip Select Signal
;//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
;//                                      <2=> 16M Bytes  <3=> 64M Bytes
;//                <i> Selects Active Bits in Base Address
;//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
;//     <o.12>     BAT: Byte Access Type <0=> Byte-write
;//                                      <1=> Byte-select
;//     <e.5>      WSE: Enable Wait State Generation
;//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
;//     </e>
;//     <o.9..11>  TDF: Data Float Output Time <0-7>
;//                <i> Number of Cycles Added after the Transfer
;//   </e>
EBI_CSR2_Val    EQU     0x20000000

;//   <e.13> Enable Chip Select 3 (CSR3)
;//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
;//                <i> Start Address for Chip Select Signal
;//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
;//                                      <2=> 16M Bytes  <3=> 64M Bytes
;//                <i> Selects Active Bits in Base Address
;//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
;//     <o.12>     BAT: Byte Access Type <0=> Byte-write
;//                                      <1=> Byte-select
;//     <e.5>      WSE: Enable Wait State Generation
;//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
;//     </e>
;//     <o.9..11>  TDF: Data Float Output Time <0-7>
;//                <i> Number of Cycles Added after the Transfer
;//   </e>
EBI_CSR3_Val    EQU     0x30000000

;//   <e.13> Enable Chip Select 4 (CSR4)
;//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
;//                <i> Start Address for Chip Select Signal
;//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
;//                                      <2=> 16M Bytes  <3=> 64M Bytes
;//                <i> Selects Active Bits in Base Address
;//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
;//     <o.12>     BAT: Byte Access Type <0=> Byte-write
;//                                      <1=> Byte-select
;//     <e.5>      WSE: Enable Wait State Generation
;//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
;//     </e>
;//     <o.9..11>  TDF: Data Float Output Time <0-7>
;//                <i> Number of Cycles Added after the Transfer
;//   </e>
EBI_CSR4_Val    EQU     0x40000000

;//   <e.13> Enable Chip Select 5 (CSR5)
;//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
;//                <i> Start Address for Chip Select Signal
;//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
;//                                      <2=> 16M Bytes  <3=> 64M Bytes
;//                <i> Selects Active Bits in Base Address
;//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
;//     <o.12>     BAT: Byte Access Type <0=> Byte-write
;//                                      <1=> Byte-select
;//     <e.5>      WSE: Enable Wait State Generation
;//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
;//     </e>
;//     <o.9..11>  TDF: Data Float Output Time <0-7>
;//                <i> Number of Cycles Added after the Transfer
;//   </e>
EBI_CSR5_Val    EQU     0x50000000

;//   <e.13> Enable Chip Select 6 (CSR6)
;//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
;//                <i> Start Address for Chip Select Signal
;//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
;//                                      <2=> 16M Bytes  <3=> 64M Bytes
;//                <i> Selects Active Bits in Base Address
;//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
;//     <o.12>     BAT: Byte Access Type <0=> Byte-write
;//                                      <1=> Byte-select
;//     <e.5>      WSE: Enable Wait State Generation
;//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
;//     </e>
;//     <o.9..11>  TDF: Data Float Output Time <0-7>
;//                <i> Number of Cycles Added after the Transfer
;//   </e>
EBI_CSR6_Val    EQU     0x60000000

;//   <e.13> Enable Chip Select 7 (CSR7)
;//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
;//                <i> Start Address for Chip Select Signal
;//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
;//                                      <2=> 16M Bytes  <3=> 64M Bytes
;//                <i> Selects Active Bits in Base Address
;//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
;//     <o.12>     BAT: Byte Access Type <0=> Byte-write
;//                                      <1=> Byte-select
;//     <e.5>      WSE: Enable Wait State Generation
;//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
;//     </e>
;//     <o.9..11>  TDF: Data Float Output Time <0-7>
;//                <i> Number of Cycles Added after the Transfer
;//   </e>
EBI_CSR7_Val    EQU     0x70000000

;//   <q.4>        DRP: Data Read Protocol
;//                     <0=> Standard Read
;//                     <1=> Early Read
EBI_MCR_Val     EQU     0x00000010

;// </h> End of EBI


; Power Mangement Controller (PMC) definitions
PMC_BASE        EQU     0xFFFF4000      ; PMC Base Address 
PMC_CGMR        EQU     0x20            ; PMC_CGMR Offset 
PMC_SR	        EQU     0x30            ; PMC_SR Offset 
PMC_MCKOSS      EQU     (3<<4)          ; Master Clock Output Selection
PMC_MCKO        EQU     (1<<6)          ; Master Clock Output Disable
PMC_PLLS        EQU     (1<<3)          ; PLL Selection
PMC_CSS         EQU     (1<<7)          ; Clock Source Selection
PMC_PRES        EQU     (7<<0)          ; Prescaler Selection
PMC_MUL         EQU     (0x7FF<<8)      ; Phase Lock Loop Factor
PMC_PLLCOUNT    EQU     (0xFF<<24)      ; PLL Lock Counter
PMC_PLL_LOCK    EQU     (1<<0)          ; PLL Lock Status 

;// <e> AT91M42800A PMC Clock Setup
;//   <o1.7>      CSS: Clock Source Selection
;//               <0=> Slow Clock
;//               <1=> PLL Output
;//   <o1.3>      PLLS: PLL Selection
;//               <0=> PLL A (5 - 20MHz)
;//               <1=> PLL B (20 - 80MHz)
;//   <o1.0..2>   PRES: Prescaler
;//               <0=> None
;//               <1=> Clock / 2    <2=> Clock / 4
;//               <3=> Clock / 8    <4=> Clock / 16
;//               <5=> Clock / 32   <6=> Clock / 64
;//   <o1.8..18>  MUL: Phase Lock Loop Factor <0-2047>
;//               <i> PLL Output is multiplied by MUL+1
;//   <o1.24..31> PLLCOUNT: PLL Lock Counter <0x0-0xFF>
;//               <i> PLL Lock Timer
;//   <o1.4..5>   MCKOSS: Master Clock Output Source Selection
;//               <0=> Slow Clock
;//               <1=> Master Clock
;//               <2=> Master Clock Inverted
;//               <3=> Master Clock / 2
;//   <q1.6>      MCKODS: Master Clock Output Disable <0-1>
;// </e>
PMC_SETUP       EQU     0
PMC_CGMR_Val    EQU     0x1003FF98


; Advanced Power Mangement Controller (APMC) definitions
APMC_BASE       EQU     0xFFFF4000      ; APMC Base Address 
APMC_CGMR       EQU     0x20            ; APMC_CGMR Offset 
APMC_SR	        EQU     0x30            ; APMC_SR Offset 
APMC_MOSC_BYP   EQU     (1<<0)          ; Main Oscillator Bypass
APMC_MOSC_EN    EQU     (1<<1)          ; Main Oscillator Enable
APMC_MCKO_DIS   EQU     (1<<2)          ; Disable Master Clock Output
APMC_CSS        EQU     (3<<14)         ; Clock Source Selection
APMC_PRES       EQU     (7<<4)          ; Prescaler Selection
APMC_MUL        EQU     (0x3F<<8)       ; Phase Lock Loop Factor
APMC_OSCOUNT    EQU     (0xFF<<16)      ; Main Oscillator Counter
APMC_PLLCOUNT   EQU     (0x3F<<24)      ; PLL Lock Counter
APMC_MOSCS      EQU     (1<<0)          ; Main Osillator Status 
APMC_PLL_LOCK   EQU     (1<<1)          ; PLL Lock Status