📄 4830wr.asm
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;mask option:
;WDT: disabled
;WDTinstr:one clear instruction
;PA wake up:noen
;pullhigh:all
;WDT OSC :on chip RC
;OSC:crystal
;sysvolt:5.000V
;sysfreq:1000kHz,internal
;product:24SKDIP_B
include ht48r30a-1.inc
; file name: 4810wr.asm
; 作者:盛扬半导体(上海)有限公司软件部
; 目的:熟悉HT48系列控制24系列单片机的流程
eeprom .section 'data'
scl equ pa.3 ;定义pa.3为时钟脚
scl_c equ pac.3
sda equ pa.1 ;定义pa.1为数据脚
sda_c equ pac.1
read_out equ [70h] ;读出数据暂存器
write_in equ [71h] ;写入数据暂存器
word_address equ [72h] ;读写地址暂存器
data_8 equ [73h]
delay_5 equ [77h]
delay equ [78h]
eepromc .section 'code'
org 00h
jmp start
org 020h
start:
mov a,55h
mov write_in,a ;写入55H
mov a,14h ;写入14H为要操作的eeprom的地址
mov word_address,a
write_data:
clr sda_c
clr scl_c
set sda
set scl
clr sda ;起始信号
clr scl
set sda ;1
set scl
clr scl
clr sda ;0
set scl
clr scl
set sda ;1
set scl
clr scl
clr sda ;0
set scl
clr scl
clr sda ;a2,a1,a0=000
set scl
clr scl
set scl
clr scl
set scl
clr scl
set scl ;写0,设定为写入模式
clr scl
set sda_c
set scl
wait_ack:
sz sda ;等待应答信号
jmp wait_ack
clr scl
clr sda_c
mov a,08h ;设传输数据长度8
mov data_8,a
random_write:
clr sda
sz word_address.7
set sda
set scl
clr scl
rl word_address
sdz data_8
jmp random_write
set sda_c
set scl
fdev:
sz sda ;等待应答信号
jmp fdev
clr scl
clr sda_c
mov a,08h
mov data_8,a
dtat_in:
clr sda
sz write_in.7
set sda
set scl
clr scl
rl write_in
sdz data_8
jmp dtat_in
set scl
clr scl
clr sda
set scl
set sda ;停止信号
mov a,30h
mov delay_5,a
mov a,05h
mov delay,a
delay1:
sdz delay_5
jmp delay1
sdz delay
jmp delay1
;_______________________________
;读
do_read:
clr read_out
clr sda_c
clr scl_c
set sda
set scl
clr sda ;起始信号
clr scl
set sda ;1
set scl
clr scl
clr sda ;0
set scl
clr scl
set sda ;1
set scl
clr scl
clr sda ;0
set scl
clr scl
clr sda
set scl ;a0,a1,a2=0
clr scl
set scl ;0
clr scl
set scl ;0
clr scl
clr sda ;写模式,写地址
set scl
clr scl
set sda_c
set scl
wait:
sz sda
jmp wait
clr scl
mov a,08h
mov data_8,a
clr sda_c
read_address_in:
clr sda
sz word_address.7
set sda
set scl
clr scl
rl word_address
sdz data_8
jmp read_address_in
set sda_c
set scl
ack:
sz sda
jmp ack
clr scl
clr sda_c
read_data:
set sda
set scl
clr sda ;start bit
clr scl
set sda ;1
set scl
clr scl
clr sda ;0
set scl
clr scl
set sda ;1
set scl
clr scl
clr sda ;0
set scl
clr scl
clr sda ;a2,a1,a0
set scl
clr scl
set scl
clr scl
set scl
clr scl
set sda ;读模式
set scl
clr scl
set sda_c
;set scl
w_ack:
sz sda
jmp w_ack
;clr scl
set scl ;down_edge data out
mov a,08h
mov data_8,a
set sda_c
random_out:
set scl
call del
clr scl
call del
rl read_out
clr read_out.0
sz sda
set read_out.0
sdz data_8
jmp random_out
mov a,read_out ;modify
mov [41h],a ;modify
clr sda_c ;for stop
set scl
set sda
clr scl
clr sda
set sda ;stop end
mov a,055h
xor a,read_out
sz acc
jmp fail_out
jmp OK_end
fail_out:
jmp $
ok_end:
jmp $
del: ;for delay
nop
nop
nop
ret
;更改:在读取数据时应该从低位存入,逐次左移
;注意:读取操作的时钟频率不应该太高
;在演示中系统时钟频率为1.5MHz,如果系统时钟频率比较高的话,
;则应该加上延时操作,否则会出现读取数据错误.
;在HT48R30A-1上通过
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