📄 mb90340.asm
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* CREATED BY IO-WIZARD V2.16 */
/* $Id: mb90340.asm,v 4.8 2004/03/26 12:34:25 dfisch Exp $ */
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES. */
/* (C) Fujitsu Microelectronics Europe GmbH */
/* ***************************************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or */
/* see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* ***************************************************************************** */
/* */
/* NOTE: */
/* */
/* This header-file will cover all features of the Emulation chip MB90V340/S. */
/* No Flash- or Mask- version of the MB90340series will support all features !!! */
/* Limitaions can be found in UARTs, CANs, I2C, ADC, etc. */
/* Please DO NOT USE resources / registers others than specified */
/* for the dedicated Flash-/Mask-version. */
/* Please refer to the datasheet and hardwaremanual of the MB90340series. */
/* */
/* */
/* ---------------------------------------------------------------------- */
/* Id: mb90340.iow,v 4.6 2004/03/26 08:47:20 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* History: */
/* Date Version Author Description */
/* 22.10.2002 1.0 HWE created (from MB90390.iow) */
/* check Register: ICS,ICE,ADC,CDMR, CANSWR */
/* 27.01.2003 1.1 HWE PPGCD is double-defined */
/* Clock-Select-Register are renamed */
/* PPG01 .. PPGCD , PPGEF */
/* => PPGCS01 .. PPGCSCD, PPGCSEF */
/* CDMR: Bit DIRECT added */
/* CANSWR: Bits TXS01, RXS01 added */
/* ADC_01_new.h corrected */
/* PRLxy Longwordaccess */
/* 03.02.2003 1.2 HWE Register DCSR: Bitdefinition corrected */
/* Register LPMCR: Bitdefinitions deleted */
/* Register PLLDIV renamed to PSCCR */
/* 11.02.2003 1.3 DFi Register DCSR: Groupdefinition DCSR removed */
/* LPMCR definition only, no declaration */
/* (Standby Cancel Failure) */
/* Id: mb90340.iow,v 4.0 2003/05/07 15:10:33 dfisch Exp */
/* - CVS and make controlled */
/* Id: mb90340.iow,v 4.1 2003/08/18 13:50:29 dfisch Exp */
/* - Register ILSR: Bitdefinition corrected, */
/* - Register ILSR: Word splitted: (ILSR0, ILSR1) */
/* - Register DDRA: Bitdefinition updated */
/* - Register DCT, DCTL, DCTH, IOA, IOAL, IOAH, DMACS: Bitdefinition updated */
/* - Register CMCR: Bitdefinition corrected */
/* - Register WDTC: Bitdefinition WT0, WT1, WTE deleted (Write-only) */
/* - Register ARSR, HACR, ECSR: Bitdefinitions deleted (Write-only) */
/* - Register TCCS0, TCCS1: Bytedefinition added: TCCSL0, TCCSH0, TCCSL1, TCCSH1 */
/* - Register WTC: Bits WTC0..2 grouped */
/* - Register PPGCx: Bitname PEx0 renamed to PEx */
/* - Register ESCR0..3: Bits LBL0..LBL1 grouped */
/* - Register BGRx: Bytedefinition renamed: BGR0x => BGRx0 , BGR1x => BGRx1 */
/* (BGR00, BGR01) (BGR10, BGR11) (BGR20, BGR21) (BGR30, BGR31) (BGR40, BGR41) */
/* - UART4 removed (SMR4, SCR4, RDR4, TDR4, SSR4, ECCR4, ESCR4, BGR4, BGR40, BGR41) */
/* - Clock Modulator removed (CMPR, CMPRL, CMPRH) */
/* - DA-Converter removed (DAT0L, DAT1L, DACR0, DACR1) */
/* Id: mb90340.iow,v 4.2 2003/08/29 12:22:20 dfisch Exp */
/* - Register DCSR: Groupdefinition DCSR defined again */
/* Id: mb90340.iow,v 4.3 2003/09/08 15:08:32 dfisch Exp */
/* - Register PPGCSxy: Bit0 (REV) added */
/* Id: mb90340.iow,v 4.4 2003/09/16 07:01:17 dfisch Exp */
/* - Address of OCCP6 (0x793C) corrected */
/* Id: mb90340.iow,v 4.5 2003/09/18 12:49:35 dfisch Exp */
/* - PRLx Wordaccess added */
/* Id: mb90340.iow,v 4.6 2004/03/26 08:47:20 dfisch Exp */
/* - ECCRx-register: Bitdefinition deleted */
/* */
/* ---------------------------------------------------------------------- */
/* Id: adc_01_new.h,v 2.2 2003/08/19 09:46:21 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* DESCRIPTION: Interrupt Control Register Declaration */
/* */
/* AUTHOR: Fujitsu Mikroelektronik GmbH */
/* */
/* HISTORY: */
/* Version 1.0 22.10.2002 : HWe, original version */
/* Version 1.1 15.01.2003 : HWe, ADCS0: Bit0 (STBY) deleted */
/* Id: adc_01_new.h,v 2.0 2003/05/06 09:00:19 dfisch Exp */
/* - CVS and make controlled */
/* Id: adc_01_new.h,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* Id: adc_01_new.h,v 2.2 2003/08/19 09:46:21 dfisch Exp */
/* - ADCS0 Bit-defs as const, only Byte-write */
/* ---------------------------------------------------------------------- */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* */
/* DESCRIPTION: Interrupt Control Register Declaration */
/* */
/* AUTHOR: Fujitsu Mikroelektronik GmbH */
/* */
/* HISTORY: */
/* Version 1.0 26.01.99: */
/* - original version */
/* Version 1.2 11.02.99 */
/* - "extern" changed to pre-defined macro of IO-Wizard */
/* (__IO_EXTERN), requires IO-Wizard 1.7 or later */
/* */
/* Version 1.3 17.07.2002 HW Bitdefinitions as const, no RMV allowed */
/* Id: ICR.H,v 2.0 2003/05/06 09:03:53 dfisch Exp */
/* - CVS and make controlled */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* ---------------------------------------------------------------------- */
/* Id: CANSTR.H,v 3.1 2003/06/27 14:30:51 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* CANIO: control structures of CAN for LX-controllers */
/* */
/* Version: 1.0 23.01.99 HL */
/* - original version */
/* Version: 2.0 26.02.99 HL */
/* - unsigned int replace by IO_WORD (FR/LX have diff int) */
/* - unsigned char replace by IO_BYTE */
/* Version: 2.1 26.08.02 HLo */
/* - const specifier used for RTEC union */
/* - REC and TEC of RTEC changed from bit group to Byte type */
/* - short type addded to DTR register for compatibility */
/* Id: CANSTR.H,v 3.0 2003/05/06 09:02:30 dfisch Exp */
/* - CVS and make controlled */
/* Id: CANSTR.H,v 3.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* ---------------------------------------------------------------------- */
/* Id: canmac012.h,v 5.0 2003/05/06 09:01:20 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* CANIO: control structures for LX-controllers */
/* version 1.0 to 2.2 for double CAN */
/* */
/* Version: 1.0 23.01.99 FMG, HLO */
/* - original version */
/* Version: 1.1 27.01.99 FMG, tka */
/* - idrx0 changed to IDRX0 */
/* Version: 1.2 11.02.99 FMG, HLO */
/* - "extern" declaration changed to predefined macros of */
/* IO-Wizard, requires IO-Wizard 1.7 or later */
/* - DRT1_LWPTR changed to DTR1_DWPTR macro */
/* Version: 2.0 28.05.01 HLO */
/* - LX-version adopted to FR */
/* - __IO_EXTENDED changed to __IO_EXTERN, CAN is on external bus */
/* Version: 2.1 08.06.01 HLO */
/* - macro for short type in DTR added */
/* Version: 2.2 11.06.01 MEN */
/* - DLC changed to IO_WORD */
/* Version: 3.0 05.08.02 DF */
/* - removed CAN1 */
/* Version: 3.1 23.08.02 DF */
/* - DTR_LWPTR and DTR_DWPTR for compatibility */
/* Version: 4.0 23.08.02 HLO */
/* - changed to batch generation */
/* Id: canmac012.h,v 5.0 2003/05/06 09:01:20 dfisch Exp */
/* - CVS and make controlled */
/* ---------------------------------------------------------------------- */
/* Id: security.asm,v 1.1 2003/08/19 10:25:24 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* Id: security.asm,v 1.1 2003/08/19 10:25:24 dfisch Exp */
/* - initial */
.PROGRAM MB90340
.TITLE MB90340
;------------------------
; IO-AREA DEFINITIONS :
;------------------------
.section IOBASE, IO, locate=0x0000 ; /* PORT DATA */
.GLOBAL __pdr0, __pdr1, __pdr2, __pdr3, __pdr4, __pdr5
.GLOBAL __pdr6, __pdr7, __pdr8, __pdr9, __pdra, __ader5
.GLOBAL __ader6, __ader7, __ilsr, __ilsr0, __ilsr1, __ddr0
.GLOBAL __ddr1, __ddr2, __ddr3, __ddr4, __ddr5, __ddr6
.GLOBAL __ddr7, __ddr8, __ddr9, __ddra, __pucr0, __pucr1
.GLOBAL __pucr2, __pucr3, __smr0, __scr0, __rdr0, __tdr0
.GLOBAL __ssr0, __eccr0, __escr0, __bgr0, __bgr00, __bgr01
.GLOBAL __smr1, __scr1, __rdr1, __tdr1, __ssr1, __eccr1
.GLOBAL __escr1, __bgr1, __bgr10, __bgr11, __ppgc01, __ppgc0
.GLOBAL __ppgc1, __ppgcs01, __ppgc23, __ppgc2, __ppgc3, __ppgcs23
.GLOBAL __ppgc45, __ppgc4, __ppgc5, __ppgcs45, __pacsr1, __ppgc67
.GLOBAL __ppgc6, __ppgc7, __ppgcs67, __ppgc89, __ppgc8, __ppgc9
.GLOBAL __ppgcs89, __ppgcab, __ppgca, __ppgcb, __ppgcsab, __ppgccd
.GLOBAL __ppgcc, __ppgcd, __ppgcscd, __ppgcef, __ppgce, __ppgcf
.GLOBAL __ppgcsef, __ics01, __ice01, __ics23, __ice23, __ics45
.GLOBAL __ice45, __ics67, __ice67, __ocs01, __ocs0, __ocs1
.GLOBAL __ocs23, __ocs2, __ocs3, __ocs45, __ocs4, __ocs5
.GLOBAL __ocs67, __ocs6, __ocs7, __tmcsr0, __tmcsr1, __tmcsr2
.GLOBAL __tmcsr3, __adcs, __adcs0, __adcs1, __adcr, __adcr0
.GLOBAL __adcr1, __adsr, __romm, __canl0, __canl1, __dcsr
.GLOBAL __dsr, __dsrl, __dsrh, __pacsr0, __dirr, __lpmcr
.GLOBAL __ckscr, __dssr, __dssr1, __dssr0, __arsr, __hacr
.GLOBAL __ecsr, __wdtc, __tbtc, __wtc, __der, __derl
.GLOBAL __derh, __fmcs, __icr, __enir0, __eirr0, __elvr0
.GLOBAL __enir1, __eirr1, __elvr1, __eissr, __psccr, __bapl
.GLOBAL __bapm, __baph, __dmacs, __ioa, __ioal, __ioah
.GLOBAL __dct, __dctl, __dcth, __smr2, __scr2, __rdr2
.GLOBAL __tdr2, __ssr2, __eccr2, __escr2, __bgr2, __bgr20
.GLOBAL __bgr21, __canl2
__pdr0 .res.b 1 ;000000 /* PORT DATA */
PDR0 .equ 0x0000
__pdr1 .res.b 1 ;000001
PDR1 .equ 0x0001
__pdr2 .res.b 1 ;000002
PDR2 .equ 0x0002
__pdr3 .res.b 1 ;000003
PDR3 .equ 0x0003
__pdr4 .res.b 1 ;000004
PDR4 .equ 0x0004
__pdr5 .res.b 1 ;000005
PDR5 .equ 0x0005
__pdr6 .res.b 1 ;000006
PDR6 .equ 0x0006
__pdr7 .res.b 1 ;000007
PDR7 .equ 0x0007
__pdr8 .res.b 1 ;000008
PDR8 .equ 0x0008
__pdr9 .res.b 1 ;000009
PDR9 .equ 0x0009
__pdra .res.b 1 ;00000A
PDRA .equ 0x000A
__ader5 .res.b 1 ;00000B
ADER5 .equ 0x000B
__ader6 .res.b 1 ;00000C
ADER6 .equ 0x000C
__ader7 .res.b 1 ;00000D
ADER7 .equ 0x000D
__ilsr .res.b 2 ;00000E
ILSR .equ 0x000E
.org 0x000E
__ilsr0 .res.b 1 ;00000E
ILSR0 .equ 0x000E
__ilsr1 .res.b 1 ;00000F
ILSR1 .equ 0x000F
__ddr0 .res.b 1 ;000010 /* PORT DIRECTION */
DDR0 .equ 0x0010
__ddr1 .res.b 1 ;000011
DDR1 .equ 0x0011
__ddr2 .res.b 1 ;000012
DDR2 .equ 0x0012
__ddr3 .res.b 1 ;000013
DDR3 .equ 0x0013
__ddr4 .res.b 1 ;000014
DDR4 .equ 0x0014
__ddr5 .res.b 1 ;000015
DDR5 .equ 0x0015
__ddr6 .res.b 1 ;000016
DDR6 .equ 0x0016
__ddr7 .res.b 1 ;000017
DDR7 .equ 0x0017
__ddr8 .res.b 1 ;000018
DDR8 .equ 0x0018
__ddr9 .res.b 1 ;000019
DDR9 .equ 0x0019
__ddra .res.b 1 ;00001A
DDRA .equ 0x001A
.org 0x001C
__pucr0 .res.b 1 ;00001C /* PULL-UP CONTROL */
PUCR0 .equ 0x001C
__pucr1 .res.b 1 ;00001D
PUCR1 .equ 0x001D
__pucr2 .res.b 1 ;00001E
PUCR2 .equ 0x001E
__pucr3 .res.b 1 ;00001F
PUCR3 .equ 0x001F
__smr0 .res.b 1 ;000020 /* UART0 */
SMR0 .equ 0x0020
__scr0 .res.b 1 ;000021
SCR0 .equ 0x0021
__rdr0 .res.b 1 ;000022
RDR0 .equ 0x0022
.org 0x0022
__tdr0 .res.b 1 ;000022
TDR0 .equ 0x0022
__ssr0 .res.b 1 ;000023
SSR0 .equ 0x0023
__eccr0 .res.b 1 ;000024
ECCR0 .equ 0x0024
__escr0 .res.b 1 ;000025
ESCR0 .equ 0x0025
__bgr0 .res.b 2 ;000026
BGR0 .equ 0x0026
.org 0x0026
__bgr00 .res.b 1 ;000026
BGR00 .equ 0x0026
__bgr01 .res.b 1 ;000027
BGR01 .equ 0x0027
__smr1 .res.b 1 ;000028 /* UART1 */
SMR1 .equ 0x0028
__scr1 .res.b 1 ;000029
SCR1 .equ 0x0029
__rdr1 .res.b 1 ;00002A
RDR1 .equ 0x002A
.org 0x002A
__tdr1 .res.b 1 ;00002A
TDR1 .equ 0x002A
__ssr1 .res.b 1 ;00002B
SSR1 .equ 0x002B
__eccr1 .res.b 1 ;00002C
ECCR1 .equ 0x002C
__escr1 .res.b 1 ;00002D
ESCR1 .equ 0x002D
__bgr1 .res.b 2 ;00002E
BGR1 .equ 0x002E
.org 0x002E
__bgr10 .res.b 1 ;00002E
BGR10 .equ 0x002E
__bgr11 .res.b 1 ;00002F
BGR11 .equ 0x002F
__ppgc01 .res.b 2 ;000030 /* PPG control */
PPGC01 .equ 0x0030
.org 0x0030
__ppgc0 .res.b 1 ;000030
PPGC0 .equ 0x0030
__ppgc1 .res.b 1 ;000031
PPGC1 .equ 0x0031
__ppgcs01 .res.b 1 ;000032
PPGCS01 .equ 0x0032
.org 0x0034
__ppgc23 .res.b 2 ;000034
PPGC23 .equ 0x0034
.org 0x0034
__ppgc2 .res.b 1 ;000034
PPGC2 .equ 0x0034
__ppgc3 .res.b 1 ;000035
PPGC3 .equ 0x0035
__ppgcs23 .res.b 1 ;000036
PPGCS23 .equ 0x0036
.org 0x0038
__ppgc45 .res.b 2 ;000038
PPGC45 .equ 0x0038
.org 0x0038
__ppgc4 .res.b 1 ;000038
PPGC4 .equ 0x0038
__ppgc5 .res.b 1 ;000039
PPGC5 .equ 0x0039
__ppgcs45 .res.b 1 ;00003A
PPGCS45 .equ 0x003A
__pacsr1 .res.b 1 ;00003B /* Rom Correction 1 */
PACSR1 .equ 0x003B
__ppgc67 .res.b 2 ;00003C
PPGC67 .equ 0x003C
.org 0x003C
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