📄 isr.lst
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190 1 bZBoardFlags.bits.dma_state = DMA_IDLE;
191 1 }
192
193 //true iso
194 void Isr_SOF(void)
195 {
196 1 ISP1581_IntClearl(int_sof|int_psof);
197 1 }
198
199 void Isr_EP0Setup(void)
200 {
201 1 // Getting Setup Packet
202 1 ISP1581_IntClearl(int_ep0set);
203 1 SetupToken_Handler();
204 1 }
205 void Isr_Ep00RxDone(unsigned char nosetup)
206 {
207 1 UCHAR i;
208 1 unsigned short len;
209 1
210 1 //ISP1581_IntClearl(int_ep0rx);
211 1 switch (bZBoardFlags.bits.DCP_state)
212 1 {
213 2 case USBFSM4DCP_DATAOUT:
214 2
215 2 if(ControlData.wLength >= ControlData.wCount)
216 2 len = ControlData.wLength - ControlData.wCount;
217 2 else
218 2 len = 0x0;
219 2
220 2 i =ISP1581_ReadControlEndpoint(ControlData.dataBuffer + ControlData.wCount, len);
221 2 ControlData.wCount += i;
222 2
223 2 if(ControlData.wCount <= ControlData.wLength && i <= EP0_PACKET_SIZE)
224 2 {
225 3 bZBoardFlags.bits.CONTROL_HANDLE_DONE = 1;
226 3 bZBoardFlags.bits.DCP_state = USBFSM4DCP_REQUESTPROC;
227 3 }
228 2 else // too much data out than expected
229 2 {
230 3 if(nosetup)
231 3 {
232 4 ISP1581_StallEP0InControlWrite();
233 4 bZBoardFlags.bits.DCP_state = USBFSM4DCP_STALL;
234 4 }
235 3 }
236 2 ISP1581_IntClearl(int_ep0rx);
237 2 break;
238 2 case USBFSM4DCP_CONTROLREADHANDSHAKE:
239 2 bZBoardFlags.bits.DCP_state = USBFSM4DCP_IDLE;
240 2 ISP1581_IntClearl(int_ep0rx);
241 2 break;
C51 COMPILER V7.06 ISR 09/09/2005 13:57:31 PAGE 5
242 2 case USBFSM4DCP_IDLE:
243 2 bZBoardFlags.bits.DCP_state = USBFSM4DCP_IDLE;
244 2 if(nosetup)
245 2 {//MCU_LED0 = 0;
246 3 ISP1581_IntClearl(int_ep0rx);}
247 2 break;
248 2 case USBFSM4DCP_STALL:
249 2 if(nosetup)
250 2 ISP1581_IntClearl(int_ep0rx);
251 2 break;
252 2 default:
253 2 if(nosetup)
254 2 {
255 3
256 3 ISP1581_StallEP0InControlWrite();
257 3 bZBoardFlags.bits.DCP_state = USBFSM4DCP_STALL;
258 3 }
259 2 break;
260 2 }
261 1 }
262 void Isr_Ep00TxDone(unsigned char nosetup)
263 {
264 1 short i;
265 1 ISP1581_IntClearl(int_ep0tx);
266 1 switch (bZBoardFlags.bits.DCP_state)
267 1 {
268 2 case USBFSM4DCP_CONTROLREADHANDSHAKE:
269 2 ISP1581_ControlReadHandshake();
270 2 bZBoardFlags.bits.DCP_state = USBFSM4DCP_CONTROLREADHANDSHAKE;
271 2 break;
272 2 case USBFSM4DCP_CONTROLWRITEHANDSHAKE:
273 2 bZBoardFlags.bits.DCP_state = USBFSM4DCP_IDLE;
274 2 break;
275 2 case USBFSM4DCP_DATAIN:
276 2 i = ControlData.wLength - ControlData.wCount;
277 2 if( i >= EP0_PACKET_SIZE)
278 2 {
279 3 ISP1581_WriteControlEndpoint(ControlData.pData + ControlData.wCount, EP0_PACKET_SIZE);
280 3 ControlData.wCount += EP0_PACKET_SIZE;
281 3 bZBoardFlags.bits.DCP_state = USBFSM4DCP_DATAIN;
282 3 }
283 2 else if( i != 0)
284 2 {
285 3 ISP1581_WriteControlEndpoint(ControlData.pData + ControlData.wCount, i);
286 3 ControlData.wCount += i;
287 3 bZBoardFlags.bits.DCP_state = USBFSM4DCP_CONTROLREADHANDSHAKE;
288 3 }
289 2 else if (i == 0)
290 2 {
291 3 ISP1581_WriteControlEndpoint(0, 0);
292 3 bZBoardFlags.bits.DCP_state = USBFSM4DCP_CONTROLREADHANDSHAKE;
293 3 }
294 2 break;
295 2 case USBFSM4DCP_STALL:
296 2 bZBoardFlags.bits.DCP_state = USBFSM4DCP_IDLE;
297 2 break;
298 2 case USBFSM4DCP_IDLE:
299 2 //MCU_LED0=0;
300 2 break;
301 2 case USBFSM4DCP_REQUESTPROC:
302 2
303 2 break;
C51 COMPILER V7.06 ISR 09/09/2005 13:57:31 PAGE 6
304 2 case USBFSM4DCP_SETUPPROC:
305 2
306 2 break;
307 2 case USBFSM4DCP_DATAOUT:
308 2
309 2 break;
310 2 default:
311 2 // do nothing, maybe just 1st nak for control in.
312 2 if(nosetup)
313 2 {
314 3 //MCU_LED0=0;
315 3 ISP1581_StallEP0InControlRead();
316 3 bZBoardFlags.bits.DCP_state = USBFSM4DCP_STALL;
317 3 }
318 2 break;
319 2
320 2 }
321 1 }
322
323 void Isr_Ep01rxDone(void)
324 {
325 1 unsigned short len;
326 1 ISP1581_IntClearl(int_ep1rx);
327 1 len= ISP1581_ReadBulkEndpoint(EPINDEX4EP01OUT,GenEpBuf,EP1_PACKET_SIZE);
328 1 writeramflag=1; //7.25
329 1 writeramlen=len;
330 1
331 1 }
332 void Isr_Ep01txDone(void)
333 {
334 1 ISP1581_IntClearl(int_ep1tx);
335 1 }
336 void Isr_Ep02rxDone(void)
337 {
338 1 unsigned short len;
339 1 ISP1581_IntClearl(int_ep2rx);
340 1 len= ISP1581_ReadBulkEndpoint(EPINDEX4EP02OUT,GenEpBuf,maxepsize_FS);
341 1
342 1 }
343 void Isr_Ep02txDone(void)
344 {
345 1 ISP1581_IntClearl(int_ep2tx);
346 1 }
347 void Isr_Ep03rxDone(void)
348 {
349 1 ISP1581_IntClearh(int_ep3rx);
350 1 }
351 void Isr_Ep03txDone(void)
352 {
353 1 ISP1581_IntClearh(int_ep3tx);
354 1 }
355 void Isr_Ep04rxDone(void)
356 {
357 1 unsigned short len;
358 1 ISP1581_IntClearh(int_ep4rx);
359 1 len= ISP1581_ReadBulkEndpoint(EPINDEX4EP04OUT,GenEpBuf,EP4_PACKET_SIZE);
360 1 ioRequest.bCommand=GenEpBuf[0];
361 1 bZBoardFlags.bits.bLED = 1;
362 1
363 1 }
364 void Isr_Ep04txDone(void)
365 {
C51 COMPILER V7.06 ISR 09/09/2005 13:57:31 PAGE 7
366 1 ISP1581_IntClearh(int_ep4tx);
367 1 }
368
369
370 ///////////////////////////////////////////////////////////////////////////
371
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 1017 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 5 15
IDATA SIZE = 64 ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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