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AT91RM9200的USB相关ACM CDC的源代码包！ AT91RM9200-BasicUSBPipe-ARM1_2-2_0.zip

<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TWI_SVREAD"></a><b>TWI_SVREAD</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVREAD">AT91C_TWI_SVREAD</a></font></td><td><b>Slave Read</b><br>0: Slave accessed in write direction, valid only if SVACC is set.<br>1: Slave accessed in read direction, valid only if SVACC is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TWI_SVACC"></a><b>TWI_SVACC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVACC">AT91C_TWI_SVACC</a></font></td><td><b>Slave Access</b><br>0: No slave access<br>1: The device address received matches the SADR register. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TWI_GCACC"></a><b>TWI_GCACC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_GCACC">AT91C_TWI_GCACC</a></font></td><td><b>General Call Access</b><br>0: No slave access<br>1: The received device address matches the general call address. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error</b><br>0: TWI_RHR has not been loaded while RXRDY was set<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_UNRE"></a><b>TWI_UNRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_UNRE">AT91C_TWI_UNRE</a></font></td><td><b>Underrun Error</b><br>0: No underrun error<br>1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TWI_NACK"></a><b>TWI_NACK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_NACK">AT91C_TWI_NACK</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="TWI_ARBLST"></a><b>TWI_ARBLST</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_ARBLST">AT91C_TWI_ARBLST</a></font></td><td><b>Arbitration Lost</b><br>0: Arbitration win<br>1: Arbitration lost; another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. Reset by read in TWI_SR.</td></tr>
</null></table>
<a name="TWI_IDR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_IDR">AT91C_TWI_IDR</a></i> 0xFFFB8028</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_TXCOMP"></a><b>TWI_TXCOMP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_TXCOMP">AT91C_TWI_TXCOMP</a></font></td><td><b>Transmission Completed</b><br>0: In master, during the length of the current frame. In slave, from START received to STOP received.<br>1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in theTWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_TXRDY"></a><b>TWI_TXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_TXRDY">AT91C_TWI_TXRDY</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.<br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TWI_SVREAD"></a><b>TWI_SVREAD</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVREAD">AT91C_TWI_SVREAD</a></font></td><td><b>Slave Read</b><br>0: Slave accessed in write direction, valid only if SVACC is set.<br>1: Slave accessed in read direction, valid only if SVACC is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TWI_SVACC"></a><b>TWI_SVACC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVACC">AT91C_TWI_SVACC</a></font></td><td><b>Slave Access</b><br>0: No slave access<br>1: The device address received matches the SADR register. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TWI_GCACC"></a><b>TWI_GCACC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_GCACC">AT91C_TWI_GCACC</a></font></td><td><b>General Call Access</b><br>0: No slave access<br>1: The received device address matches the general call address. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error</b><br>0: TWI_RHR has not been loaded while RXRDY was set<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_UNRE"></a><b>TWI_UNRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_UNRE">AT91C_TWI_UNRE</a></font></td><td><b>Underrun Error</b><br>0: No underrun error<br>1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TWI_NACK"></a><b>TWI_NACK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_NACK">AT91C_TWI_NACK</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="TWI_ARBLST"></a><b>TWI_ARBLST</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_ARBLST">AT91C_TWI_ARBLST</a></font></td><td><b>Arbitration Lost</b><br>0: Arbitration win<br>1: Arbitration lost; another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. Reset by read in TWI_SR.</td></tr>
</null></table>
<a name="TWI_IMR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_IMR">AT91C_TWI_IMR</a></i> 0xFFFB802C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_TXCOMP"></a><b>TWI_TXCOMP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_TXCOMP">AT91C_TWI_TXCOMP</a></font></td><td><b>Transmission Completed</b><br>0: In master, during the length of the current frame. In slave, from START received to STOP received.<br>1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in theTWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_TXRDY"></a><b>TWI_TXRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_TXRDY">AT91C_TWI_TXRDY</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.<br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TWI_SVREAD"></a><b>TWI_SVREAD</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVREAD">AT91C_TWI_SVREAD</a></font></td><td><b>Slave Read</b><br>0: Slave accessed in write direction, valid only if SVACC is set.<br>1: Slave accessed in read direction, valid only if SVACC is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TWI_SVACC"></a><b>TWI_SVACC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_SVACC">AT91C_TWI_SVACC</a></font></td><td><b>Slave Access</b><br>0: No slave access<br>1: The device address received matches the SADR register. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TWI_GCACC"></a><b>TWI_GCACC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_GCACC">AT91C_TWI_GCACC</a></font></td><td><b>General Call Access</b><br>0: No slave access<br>1: The received device address matches the general call address. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error</b><br>0: TWI_RHR has not been loaded while RXRDY was set<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_UNRE"></a><b>TWI_UNRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_UNRE">AT91C_TWI_UNRE</a></font></td><td><b>Underrun Error</b><br>0: No underrun error<br>1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TWI_NACK"></a><b>TWI_NACK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_NACK">AT91C_TWI_NACK</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="TWI_ARBLST"></a><b>TWI_ARBLST</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_TWI_ARBLST">AT91C_TWI_ARBLST</a></font></td><td><b>Arbitration Lost</b><br>0: Arbitration win<br>1: Arbitration lost; another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. Reset by read in TWI_SR.</td></tr>
</null></table>
<a name="TWI_RHR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_RHR  <i>Receive Holding Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_RHR">AT91C_TWI_RHR</a></i> 0xFFFB8030</font></null></ul><br>Master or Slave Receive Holding Data<a name="TWI_THR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> TWI_THR  <i>Transmit Holding Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91RM9200_h.html#AT91C_TWI_THR">AT91C_TWI_THR</a></i> 0xFFFB8034</font></null></ul><br>Master or Slave Transmit Holding Data</null><hr></html>