at91rm9200_emac.html

AT91RM9200的USB相关ACM CDC的源代码包！ AT91RM9200-BasicUSBPipe-ARM1_2-2_0.zip

<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_RCOM"></a><b>EMAC_RCOM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RCOM">AT91C_EMAC_RCOM</a></font></td><td><b></b><br>Receive complete. A frame has been stored in memory. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RBNA"></a><b>EMAC_RBNA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RBNA">AT91C_EMAC_RBNA</a></font></td><td><b></b><br>Receive buffer not available. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TOVR"></a><b>EMAC_TOVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TOVR">AT91C_EMAC_TOVR</a></font></td><td><b></b><br>Transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_TUND"></a><b>EMAC_TUND</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TUND">AT91C_EMAC_TUND</a></font></td><td><b></b><br>Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_RTRY"></a><b>EMAC_RTRY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RTRY">AT91C_EMAC_RTRY</a></font></td><td><b></b><br>Transmit error. Retry limit exceeded. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_TBRE"></a><b>EMAC_TBRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TBRE">AT91C_EMAC_TBRE</a></font></td><td><b></b><br>Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_TCOM"></a><b>EMAC_TCOM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TCOM">AT91C_EMAC_TCOM</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="EMAC_TIDLE"></a><b>EMAC_TIDLE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TIDLE">AT91C_EMAC_TIDLE</a></font></td><td><b></b><br>Transmit idle. Set when all frames have been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_LINK"></a><b>EMAC_LINK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_LINK">AT91C_EMAC_LINK</a></font></td><td><b></b><br>Set when LINK pin changes value. Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_ROVR"></a><b>EMAC_ROVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_ROVR">AT91C_EMAC_ROVR</a></font></td><td><b></b><br>RX overrun. Set when the RX overrun status bit is set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_HRESP"></a><b>EMAC_HRESP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_HRESP">AT91C_EMAC_HRESP</a></font></td><td><b></b><br>HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.</td></tr>
</null></table>
<a name="EMAC_IMR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_IMR">AT91C_EMAC_IMR</a></i> 0xFFFBC030</font></null></ul><br>Important Note: The interrupt is masked (disabled) when the corresponding bit is set. This is non-standard for AT91 products as generally a mask bit set enables the interrupt.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_DONE"></a><b>EMAC_DONE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_DONE">AT91C_EMAC_DONE</a></font></td><td><b></b><br>Management done. The PHY maintenance register has completed its operation. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_RCOM"></a><b>EMAC_RCOM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RCOM">AT91C_EMAC_RCOM</a></font></td><td><b></b><br>Receive complete. A frame has been stored in memory. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RBNA"></a><b>EMAC_RBNA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RBNA">AT91C_EMAC_RBNA</a></font></td><td><b></b><br>Receive buffer not available. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TOVR"></a><b>EMAC_TOVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TOVR">AT91C_EMAC_TOVR</a></font></td><td><b></b><br>Transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_TUND"></a><b>EMAC_TUND</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TUND">AT91C_EMAC_TUND</a></font></td><td><b></b><br>Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_RTRY"></a><b>EMAC_RTRY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RTRY">AT91C_EMAC_RTRY</a></font></td><td><b></b><br>Transmit error. Retry limit exceeded. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_TBRE"></a><b>EMAC_TBRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TBRE">AT91C_EMAC_TBRE</a></font></td><td><b></b><br>Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_TCOM"></a><b>EMAC_TCOM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TCOM">AT91C_EMAC_TCOM</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="EMAC_TIDLE"></a><b>EMAC_TIDLE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TIDLE">AT91C_EMAC_TIDLE</a></font></td><td><b></b><br>Transmit idle. Set when all frames have been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_LINK"></a><b>EMAC_LINK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_LINK">AT91C_EMAC_LINK</a></font></td><td><b></b><br>Set when LINK pin changes value. Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_ROVR"></a><b>EMAC_ROVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_ROVR">AT91C_EMAC_ROVR</a></font></td><td><b></b><br>RX overrun. Set when the RX overrun status bit is set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_HRESP"></a><b>EMAC_HRESP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_HRESP">AT91C_EMAC_HRESP</a></font></td><td><b></b><br>HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.</td></tr>
</null></table>
<a name="EMAC_MAN"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_MAN  <i>PHY Maintenance Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_MAN">AT91C_EMAC_MAN</a></i> 0xFFFBC034</font></null></ul><br>Writing to this register starts the shift register that controls the serial connection to the PHY. On each shift cycle the MDIO pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register.<br>When read, gives current shifted value.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="EMAC_DATA"></a><b>EMAC_DATA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_DATA">AT91C_EMAC_DATA</a></font></td><td><b></b><br>For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17..16</td><td align="CENTER"><a name="EMAC_CODE"></a><b>EMAC_CODE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_CODE">AT91C_EMAC_CODE</a></font></td><td><b></b><br>Must be written to 10 in accordance with IEEE standard 802.3. Reads as written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..18</td><td align="CENTER"><a name="EMAC_REGA"></a><b>EMAC_REGA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_REGA">AT91C_EMAC_REGA</a></font></td><td><b></b><br>Register address. Specifies the register in the PHY to access.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">27..23</td><td align="CENTER"><a name="EMAC_PHYA"></a><b>EMAC_PHYA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_PHYA">AT91C_EMAC_PHYA</a></font></td><td><b></b><br>PHY address. Normally is 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29..28</td><td align="CENTER"><a name="EMAC_RW"></a><b>EMAC_RW</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RW">AT91C_EMAC_RW</a></font></td><td><b></b><br>Read/write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="EMAC_HIGH"></a><b>EMAC_HIGH</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_HIGH">AT91C_EMAC_HIGH</a></font></td><td><b></b><br>Must be written with 1 to make a valid PHY management frame. Conforms with IEEE standard 802.3.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="EMAC_LOW"></a><b>EMAC_LOW</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_LOW">AT91C_EMAC_LOW</a></font></td><td><b></b><br>Must be written with 0 to make a valid PHY management frame. Conforms with IEEE standard 802.3.</td></tr>
</null></table>
<a name="EMAC_FRA"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_FRA  <i>Frames Transmitted OK Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_FRA">AT91C_EMAC_FRA</a></i> 0xFFFBC040</font></null></ul><br>A 24-bit register counting the number of frames successfully transmitted.<a name="EMAC_SCOL"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SCOL  <i>Single Collision Frame Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SCOL">AT91C_EMAC_SCOL</a></i> 0xFFFBC044</font></null></ul><br>A 16-bit register counting the number of frames experiencing a single collision before being transmitted and experiencing no carrier loss nor underrun.<a name="EMAC_MCOL"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_MCOL  <i>Multiple Collision Frame Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_MCOL">AT91C_EMAC_MCOL</a></i> 0xFFFBC048</font></null></ul><br>A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun).<a name="EMAC_OK"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_OK  <i>Frames Received OK Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_OK">AT91C_EMAC_OK</a></i> 0xFFFBC04C</font></null></ul><br>A 24-bit register counting the number of good frames received, i.e., address recognized. A good frame is of length 64 to 1518 bytes and has no FCS, alignment or code errors.<a name="EMAC_SEQE"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SEQE  <i>Frame Check Sequence Error Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SEQE">AT91C_EMAC_SEQE</a></i> 0xFFFBC050</font></null></ul><br>ETH_SEQE An 8-bit register counting address-recognized frames that are an integral number of bytes long, that have bad CRC and that are 64 to 1518 bytes long.<a name="EMAC_ALE"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_ALE  <i>Alignment Error Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_ALE">AT91C_EMAC_ALE</a></i> 0xFFFBC054</font></null></ul><br>ETH_ALE An 8-bit register counting frames that:<br>- are address-recognized,<br>- are not an integral number of bytes long,<br>- have bad CRC when their length is truncated to an integral number of bytes,<br>- are between 64 and 1518 bytes long.<a name="EMAC_DTE"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_DTE  <i>Deferred Transmission Frame Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_DTE">AT91C_EMAC_DTE</a></i> 0xFFFBC058</font></null></ul><br>A 16-bit register counting the number of frames experiencing deferral due to carrier sense active on their first attempt at transmission (no underrun or collision).<a name="EMAC_LCOL"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_LCOL  <i>Late Collision Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_LCOL">AT91C_EMAC_LCOL</a></i> 0xFFFBC05C</font></null></ul><br>An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. No carrier loss or underrun. A late collision is counted twice, i.e., both as a collision and a late collision.<a name="EMAC_ECOL"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_ECOL  <i>Excessive Collision Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_ECOL">AT91C_EMAC_ECOL</a></i> 0xFFFBC060</font></null></ul><br>An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or underrun).<a name="EMAC_CSE"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_CSE  <i>Carrier Sense Error Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_CSE">AT91C_EMAC_CSE</a></i> 0xFFFBC064</font></null></ul><br>An 8-bit register counting the number of frames for which carrier sense was not detected and that were maintained in half-duplex mode one slot time (512 bits) after the start of transmission (no excessive collision).<a name="EMAC_TUE"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_TUE  <i>Transmit Underrun Error Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_TUE">AT91C_EMAC_TUE</a></i> 0xFFFBC068</font></null></ul><br>An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other register is incremented.<a name="EMAC_CDE"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_CDE  <i>Code Error Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_CDE">AT91C_EMAC_CDE</a></i> 0xFFFBC06C</font></null></ul><br>An 8-bit register counting the number of frames that are address-recognized, had RXER asserted during reception. If this counter is incremented, then no other counters are incremented.<a name="EMAC_ELR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_ELR  <i>Excessive Length Error Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_ELR">AT91C_EMAC_ELR</a></i> 0xFFFBC070</font></null></ul><br>8-bit register counting the number of frames received exceeding 1518 bytes in length but that do not have either a CRC error, an alignment error or a code error.<a name="EMAC_RJB"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_RJB  <i>Receive Jabber Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_RJB">AT91C_EMAC_RJB</a></i> 0xFFFBC074</font></null></ul><br>An 8-bit register counting the number of frames received exceeding 1518 bytes in length and having either a CRC error, an alignment error or a code error.<a name="EMAC_USF"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_USF  <i>Undersize Frame Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_USF">AT91C_EMAC_USF</a></i> 0xFFFBC078</font></null></ul><br>An 8-bit register counting the number of frames received less that are than 64 bytes in length but that do not have either a CRC error, an alignment error or a code error.<a name="EMAC_SQEE"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SQEE  <i>SQE Test Error Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SQEE">AT91C_EMAC_SQEE</a></i> 0xFFFBC07C</font></null></ul><br>An 8-bit register counting the number of frames where pin ECOL was not asserted within a slot time of pin ETXEN being deasserted.<a name="EMAC_DRFC"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_DRFC  <i>Discarded RX Frame Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_DRFC">AT91C_EMAC_DRFC</a></i> 0xFFFBC080</font></null></ul><br>Discarded RX Frame Register ETH_DRFC This 16-bit counter is incremented every time an address-recognized frame is received but cannot be copied to memory because the receive buffer is available.<a name="EMAC_HSH"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_HSH  <i>Hash Address High[63:32]</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_HSH">AT91C_EMAC_HSH</a></i> 0xFFFBC090</font></null></ul><br>Hash address bits 63 to 32<a name="EMAC_HSL"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_HSL  <i>Hash Address Low[31:0]</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_HSL">AT91C_EMAC_HSL</a></i> 0xFFFBC094</font></null></ul><br>Hash address bits 31 to 0<a name="EMAC_SA1L"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SA1L  <i>Specific Address 1 Low, First 4 bytes</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SA1L">AT91C_EMAC_SA1L</a></i> 0xFFFBC098</font></null></ul><br>Unicast address bits 31 to 0<a name="EMAC_SA1H"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SA1H  <i>Specific Address 1 High, Last 2 bytes</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SA1H">AT91C_EMAC_SA1H</a></i> 0xFFFBC09C</font></null></ul><br>Unicast address bits 47 to 32<a name="EMAC_SA2L"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SA2L  <i>Specific Address 2 Low, First 4 bytes</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SA2L">AT91C_EMAC_SA2L</a></i> 0xFFFBC0A0</font></null></ul><br>Unicast address bits 31 to 0<a name="EMAC_SA2H"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SA2H  <i>Specific Address 2 High, Last 2 bytes</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SA2H">AT91C_EMAC_SA2H</a></i> 0xFFFBC0A4</font></null></ul><br>Unicast address bits 47 to 32<a name="EMAC_SA3L"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SA3L  <i>Specific Address 3 Low, First 4 bytes</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SA3L">AT91C_EMAC_SA3L</a></i> 0xFFFBC0A8</font></null></ul><br>Unicast address bits 31 to 0<a name="EMAC_SA3H"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SA3H  <i>Specific Address 3 High, Last 2 bytes</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SA3H">AT91C_EMAC_SA3H</a></i> 0xFFFBC0AC</font></null></ul><br>Unicast address bits 47 to 32<a name="EMAC_SA4L"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SA4L  <i>Specific Address 4 Low, First 4 bytes</i></h4><ul><null