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AT91RM9200的USB相关ACM CDC的源代码包！ AT91RM9200-BasicUSBPipe-ARM1_2-2_0.zip

<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_CSR"></a><b>EMAC_CSR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_CSR">AT91C_EMAC_CSR</a></font></td><td><b>Clear statistics registers. </b><br>This bit is write-only. Writing a one clears the statistics registers.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_ISR"></a><b>EMAC_ISR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_ISR">AT91C_EMAC_ISR</a></font></td><td><b>Increment statistics registers. </b><br>This bit is write-only. Writing a one increments all the statistics registers by one for test purposes.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_WES"></a><b>EMAC_WES</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_WES">AT91C_EMAC_WES</a></font></td><td><b>Write enable for statistics registers. </b><br>Setting this bit to one makes the statistics registers writable for functional test purposes.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="EMAC_BP"></a><b>EMAC_BP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_BP">AT91C_EMAC_BP</a></font></td><td><b>Back pressure. </b><br>If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern).</td></tr>
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<a name="EMAC_CFG"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_CFG  <i>Network Configuration Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_CFG">AT91C_EMAC_CFG</a></i> 0xFFFBC004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_SPD"></a><b>EMAC_SPD</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_SPD">AT91C_EMAC_SPD</a></font></td><td><b>Speed. </b><br>Set to 1 to indicate 100 Mbit/sec. operation, 0 for 10 Mbit/sec. Has no other functional effect.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_FD"></a><b>EMAC_FD</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_FD">AT91C_EMAC_FD</a></font></td><td><b>Full duplex. </b><br>If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_BR"></a><b>EMAC_BR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_BR">AT91C_EMAC_BR</a></font></td><td><b>Bit rate. </b><br>Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_CAF"></a><b>EMAC_CAF</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_CAF">AT91C_EMAC_CAF</a></font></td><td><b>Copy all frames. </b><br>When set to 1, all valid frames are received.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_NBC"></a><b>EMAC_NBC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_NBC">AT91C_EMAC_NBC</a></font></td><td><b>No broadcast. </b><br>When set to 1, frames addressed to the broadcast address of all ones are not received.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_MTI"></a><b>EMAC_MTI</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_MTI">AT91C_EMAC_MTI</a></font></td><td><b>Multicast hash enable</b><br>When set multicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_UNI"></a><b>EMAC_UNI</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_UNI">AT91C_EMAC_UNI</a></font></td><td><b>Unicast hash enable. </b><br>When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="EMAC_BIG"></a><b>EMAC_BIG</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_BIG">AT91C_EMAC_BIG</a></font></td><td><b>Receive 1522 bytes. </b><br>When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_EAE"></a><b>EMAC_EAE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_EAE">AT91C_EMAC_EAE</a></font></td><td><b>External address match enable. </b><br>Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..10</td><td align="CENTER"><a name="EMAC_CLK"></a><b>EMAC_CLK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_CLK">AT91C_EMAC_CLK</a></font></td><td><b></b><br>The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="EMAC_CLK_HCLK_8"></a><b>EMAC_CLK_HCLK_8</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_EMAC_CLK_HCLK_8">AT91C_EMAC_CLK_HCLK_8</a></font></td><td><br>HCLK divided by 8</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="EMAC_CLK_HCLK_16"></a><b>EMAC_CLK_HCLK_16</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_EMAC_CLK_HCLK_16">AT91C_EMAC_CLK_HCLK_16</a></font></td><td><br>HCLK divided by 16</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="EMAC_CLK_HCLK_32"></a><b>EMAC_CLK_HCLK_32</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_EMAC_CLK_HCLK_32">AT91C_EMAC_CLK_HCLK_32</a></font></td><td><br>HCLK divided by 32</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="EMAC_CLK_HCLK_64"></a><b>EMAC_CLK_HCLK_64</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_EMAC_CLK_HCLK_64">AT91C_EMAC_CLK_HCLK_64</a></font></td><td><br>HCLK divided by 64</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="EMAC_RTY"></a><b>EMAC_RTY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RTY">AT91C_EMAC_RTY</a></font></td><td><b></b><br>Retry test. When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="EMAC_RMII"></a><b>EMAC_RMII</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RMII">AT91C_EMAC_RMII</a></font></td><td><b></b><br>When set, this bit enables the RMII operation mode. When reset, it selects the MII mode.</td></tr>
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<a name="EMAC_SR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_SR  <i>Network Status Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_SR">AT91C_EMAC_SR</a></i> 0xFFFBC008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_MDIO"></a><b>EMAC_MDIO</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_MDIO">AT91C_EMAC_MDIO</a></font></td><td><b></b><br>0 = MDIO pin is not set<br>1 = MDIO pin set</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_IDLE"></a><b>EMAC_IDLE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_IDLE">AT91C_EMAC_IDLE</a></font></td><td><b></b><br>0 = PHY logic is idle<br>1 = PHY logic is running</td></tr>
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<a name="EMAC_TAR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_TAR  <i>Transmit Address Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_TAR">AT91C_EMAC_TAR</a></i> 0xFFFBC00C</font></null></ul><br>Transmit address register. Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the transmit FIFO. Note that if the two least significant bits are not zero, transmit starts at the byte indicated.<a name="EMAC_TCR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_TCR  <i>Transmit Control Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_TCR">AT91C_EMAC_TCR</a></i> 0xFFFBC010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">10..0</td><td align="CENTER"><a name="EMAC_LEN"></a><b>EMAC_LEN</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_LEN">AT91C_EMAC_LEN</a></font></td><td><b></b><br>Transmit frame length. This register is written to the number of bytes to be transmitted excluding the four CRC bytes unless the no CRC bit is asserted. Writing these bits to any non-zero value initiates a transmission. If the value is greater than 1514 (1518 if no CRC is being generated), an oversize frame is transmitted. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Must always be written in address-then-length order. Reads as the total number of bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) Frame transmis-sion does not start until two 32-bit words have been loaded into the transmit FIFO. The length must be great enough to ensure two words are loaded.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="EMAC_NCRC"></a><b>EMAC_NCRC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_NCRC">AT91C_EMAC_NCRC</a></font></td><td><b></b><br>No CRC. If this bit is set, it is assumed that the CRC is included in the length being written in the low-order bits and the MAC does not append CRC to the transmitted frame. If the buffer is not at least 64 bytes long, a short frame is sent. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Reads as the value of the frame currently being transmitted.</td></tr>
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<a name="EMAC_TSR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_TSR  <i>Transmit Status Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_TSR">AT91C_EMAC_TSR</a></i> 0xFFFBC014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_OVR"></a><b>EMAC_OVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_OVR">AT91C_EMAC_OVR</a></font></td><td><b></b><br>Ethernet transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when bit BNQ was not set. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_COL"></a><b>EMAC_COL</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_COL">AT91C_EMAC_COL</a></font></td><td><b></b><br>Collision occurred. Set by the assertion of collision. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RLE"></a><b>EMAC_RLE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RLE">AT91C_EMAC_RLE</a></font></td><td><b></b><br>Retry limit exceeded. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TXIDLE"></a><b>EMAC_TXIDLE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TXIDLE">AT91C_EMAC_TXIDLE</a></font></td><td><b></b><br>Transmitter Idle. Asserted when the transmitter has no frame to transmit. Cleared when a length is written to transmit frame length portion of the Transmit Control register. This bit is read-only.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_BNQ"></a><b>EMAC_BNQ</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_BNQ">AT91C_EMAC_BNQ</a></font></td><td><b></b><br>Ethernet transmit buffer not queued. Software may write a new buffer address and length to the transmit DMA controller when set. Cleared by having one frame ready to transmit and another in the process of being transmitted. This bit is read-only.</td></tr>