seedvpm642_vcapparamscif.c

ｄｓｐ平台的一路采集显示算法源码。详细介绍路采集显示。

/*
 *  Copyright 2003 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *  
 */
/* "@(#) DDK 1.10.00.21 06-26-03 (ddk-b10)" */
#include  <std.h>
#include <csl_i2c.h>
#include <vport.h>
#include <vportcap.h>
#include <tvp51xx.h> 
#include <csl_edma.h>
#include "seedvpm642_vcapparams.h"
#include "seeddm642.h"

#define LINE_SZ   384
#define NUM_LINES 144

VPORTCAP_Params SEEDVPM642_vCapParamsChan = {
    VPORT_MODE_BT656_8BIT, /* cmode:3  */
    VPORT_FLDOP_FRAME,     /* fldOp:3  */    

    VPORT_SCALING_DISABLE, /* scale:1  */    
    VPORT_RESMPL_DISABLE,  /* resmpl:1 */
    VPORTCAP_BPK_10BIT_ZERO_EXTENDED, /*bpk10Bit:2   */

    VPORTCAP_HRST_SAV,     /*hCtRst:1  */
    VPORTCAP_VRST_EAV_V0,  /*vCtRst:1  */
    VPORTCAP_FLDD_DISABLE, /*fldDect:1 */
    VPORTCAP_EXC_DISABLE,  /*extCtl:1  */   
    VPORTCAP_FINV_ENABLE,  /* fldInv:1 */
    
    80,                     /*fldXStrt1 */
    80,                     /*fldYStrt1 */  
    80,                     /*fldXStrt2 */  
    80, //15,               /*fldYStrt2 */
    
    LINE_SZ-1+80,             /*fldXStop1 */
    NUM_LINES+80, //+14,      /*fldYStop1 */
    
    LINE_SZ-1+80,             /*fldXStop2 */
    NUM_LINES+80, //+14,    /*fldYStop2 */
    
    (LINE_SZ>>3),          /*thrld     */
    3,                     /*numFrmBufs*/
    128,                     /*alignment */
    VPORT_FLDS_MERGED,     /*mergeFlds */
    NULL,                  /*segId     */            
    EDMA_OPT_PRI_HIGH,     /*edmaPri   */
    8                      /* irqId    */
};

VPORTCAP_Params SEEDVPM642_vCapParamsChan2a = {
    VPORT_MODE_BT656_8BIT, /* cmode:3  */
    VPORT_FLDOP_FRAME,     /* fldOp:3  */    

    VPORT_SCALING_DISABLE, /* scale:1  */    
    VPORT_RESMPL_DISABLE,  /* resmpl:1 */
    VPORTCAP_BPK_10BIT_ZERO_EXTENDED, /*bpk10Bit:2   */

    VPORTCAP_HRST_SAV,     /*hCtRst:1  */
    VPORTCAP_VRST_EAV_V0,  /*vCtRst:1  */
    VPORTCAP_FLDD_DISABLE, /*fldDect:1 */
    VPORTCAP_EXC_DISABLE,  /*extCtl:1  */   
    VPORTCAP_FINV_ENABLE,  /* fldInv:1 */
    
    80,                     /*fldXStrt1 */
    80,                     /*fldYStrt1 */  
    80,                     /*fldXStrt2 */  
    80, //15,               /*fldYStrt2 */
    
    LINE_SZ-1+80,             /*fldXStop1 */
    NUM_LINES+80, //+14,      /*fldYStop1 */
    
    LINE_SZ-1+80,             /*fldXStop2 */
    NUM_LINES+80, //+14,      /*fldYStop2 */
    
    (LINE_SZ>>3),          /*thrld     */
    3,                     /*numFrmBufs*/
    128,                     /*alignment */
    VPORT_FLDS_MERGED,     /*mergeFlds */
    NULL,                  /*segId     */            
    EDMA_OPT_PRI_HIGH,     /*edmaPri   */
    9                      /* irqId    */
};
VPORTCAP_Params SEEDVPM642_vCapParamsChan2b = {
    VPORT_MODE_BT656_8BIT, /* cmode:3  */
    VPORT_FLDOP_FRAME,     /* fldOp:3  */    

    VPORT_SCALING_DISABLE, /* scale:1  */    
    VPORT_RESMPL_DISABLE,  /* resmpl:1 */
    VPORTCAP_BPK_10BIT_ZERO_EXTENDED, /*bpk10Bit:2   */

    VPORTCAP_HRST_SAV,     /*hCtRst:1  */
    VPORTCAP_VRST_EAV_V0,  /*vCtRst:1  */
    VPORTCAP_FLDD_DISABLE, /*fldDect:1 */
    VPORTCAP_EXC_DISABLE,  /*extCtl:1  */   
    VPORTCAP_FINV_ENABLE,  /* fldInv:1 */
    
    80,                     /*fldXStrt1 */
    80,                     /*fldYStrt1 */  
    80,                     /*fldXStrt2 */  
    80, //15,               /*fldYStrt2 */
    
    LINE_SZ-1+80,             /*fldXStop1 */
    NUM_LINES+80, //+14,      /*fldYStop1 */
    
    LINE_SZ-1+80,             /*fldXStop2 */
    NUM_LINES+80, //+14,      /*fldYStop2 */
    
    (LINE_SZ>>3),          /*thrld     */
    3,                     /*numFrmBufs*/
    128,                     /*alignment */
    VPORT_FLDS_MERGED,     /*mergeFlds */
    NULL,                  /*segId     */            
    EDMA_OPT_PRI_HIGH,     /*edmaPri   */
    14                      /* irqId    */
};


VPORT_PortParams SEEDVPM642_vCapParamsPort = {
    FALSE,                      /*  enableDualChan;                */ 
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 1 polarity    */
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 2 polarity    */
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 3 polarity    */
    &TVP51XX_Fxns,
    INV,
};
VPORT_PortParams SEEDVPM642_vCapParamsPortCh2a = {
    TRUE ,                      /*  enableDualChan;                */ 
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 1 polarity    */
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 2 polarity    */
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 3 polarity    */
    &TVP51XX_Fxns,
    &TVP51XX_Fxns,
};
VPORT_PortParams SEEDVPM642_vCapParamsPortCh2b = {
    TRUE,                      /*  enableDualChan;                */ 
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 1 polarity    */
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 2 polarity    */
    VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 3 polarity    */
    &TVP51XX_Fxns,
    &TVP51XX_Fxns,
};    

TVP51XX_ConfParams SEEDVPM642_vCapParamsTVP5150 = {
  	TVP51XX_MODE_PAL601,	/*TVP5150的视频模式*/
  	TVP51XX_AFMT_COMPOSITE,	/*TVP5150的输入方式*/
  	1,						/*input port*/
	};						/*handleI2C */