synp.tan.rpt

三端口输入

+-------+--------------+------------+--------+-----------+----------+
; N/A   ; None         ; 2.909 ns   ; syndin ; synp~reg0 ; clk      ;
; N/A   ; None         ; 2.625 ns   ; syndin ; syndin1   ; clk      ;
; N/A   ; None         ; 2.132 ns   ; enab   ; synp~reg0 ; clk      ;
+-------+--------------+------------+--------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 7.392 ns   ; synp~reg0 ; synp ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+--------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To        ; To Clock ;
+---------------+-------------+-----------+--------+-----------+----------+
; N/A           ; None        ; -2.007 ns ; enab   ; synp~reg0 ; clk      ;
; N/A           ; None        ; -2.500 ns ; syndin ; syndin1   ; clk      ;
; N/A           ; None        ; -2.784 ns ; syndin ; synp~reg0 ; clk      ;
+---------------+-------------+-----------+--------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Dec 26 15:03:32 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off synp -c synp --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 390.02 MHz between source register "syndin1" and destination register "synp~reg0"
    Info: fmax restricted to clock pin edge rate 2.564 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.167 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y1_N2; Fanout = 1; REG Node = 'syndin1'
            Info: 2: + IC(0.497 ns) + CELL(0.670 ns) = 1.167 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'
            Info: Total cell delay = 0.670 ns ( 57.41 % )
            Info: Total interconnect delay = 0.497 ns ( 42.59 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.660 ns
                Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'
                Info: Total cell delay = 1.519 ns ( 41.50 % )
                Info: Total interconnect delay = 2.141 ns ( 58.50 % )
            Info: - Longest clock path from clock "clk" to source register is 3.660 ns
                Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N2; Fanout = 1; REG Node = 'syndin1'
                Info: Total cell delay = 1.519 ns ( 41.50 % )
                Info: Total interconnect delay = 2.141 ns ( 58.50 % )
        Info: + Micro clock to output delay of source is 0.202 ns
        Info: + Micro setup delay of destination is 0.011 ns
Info: tsu for register "synp~reg0" (data pin = "syndin", clock pin = "clk") is 2.909 ns
    Info: + Longest pin to register delay is 6.558 ns
        Info: 1: + IC(0.000 ns) + CELL(1.312 ns) = 1.312 ns; Loc. = PIN_AD22; Fanout = 2; PIN Node = 'syndin'
        Info: 2: + IC(4.684 ns) + CELL(0.562 ns) = 6.558 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'
        Info: Total cell delay = 1.874 ns ( 28.58 % )
        Info: Total interconnect delay = 4.684 ns ( 71.42 % )
    Info: + Micro setup delay of destination is 0.011 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.660 ns
        Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'
        Info: Total cell delay = 1.519 ns ( 41.50 % )
        Info: Total interconnect delay = 2.141 ns ( 58.50 % )
Info: tco from clock "clk" to destination pin "synp" through register "synp~reg0" is 7.392 ns
    Info: + Longest clock path from clock "clk" to source register is 3.660 ns
        Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'
        Info: Total cell delay = 1.519 ns ( 41.50 % )
        Info: Total interconnect delay = 2.141 ns ( 58.50 % )
    Info: + Micro clock to output delay of source is 0.202 ns
    Info: + Longest register to pin delay is 3.530 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'
        Info: 2: + IC(1.035 ns) + CELL(2.495 ns) = 3.530 ns; Loc. = PIN_AC24; Fanout = 0; PIN Node = 'synp'
        Info: Total cell delay = 2.495 ns ( 70.68 % )
        Info: Total interconnect delay = 1.035 ns ( 29.32 % )
Info: th for register "synp~reg0" (data pin = "enab", clock pin = "clk") is -2.007 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.660 ns
        Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'
        Info: Total cell delay = 1.519 ns ( 41.50 % )
        Info: Total interconnect delay = 2.141 ns ( 58.50 % )
    Info: + Micro hold delay of destination is 0.114 ns
    Info: - Shortest pin to register delay is 5.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.490 ns) = 1.490 ns; Loc. = PIN_AD25; Fanout = 1; PIN Node = 'enab'
        Info: 2: + IC(4.021 ns) + CELL(0.270 ns) = 5.781 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'
        Info: Total cell delay = 1.760 ns ( 30.44 % )
        Info: Total interconnect delay = 4.021 ns ( 69.56 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Dec 26 15:03:33 2005
    Info: Elapsed time: 00:00:01