📄 synp.tan.qmsg

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💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "synp~reg0 syndin clk 2.909 ns register " "Info: tsu for register \"synp~reg0\" (data pin = \"syndin\", clock pin = \"clk\") is 2.909 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.558 ns + Longest pin register " "Info: + Longest pin to register delay is 6.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.312 ns) 1.312 ns syndin 1 PIN PIN_AD22 2 " "Info: 1: + IC(0.000 ns) + CELL(1.312 ns) = 1.312 ns; Loc. = PIN_AD22; Fanout = 2; PIN Node = 'syndin'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { syndin } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.684 ns) + CELL(0.562 ns) 6.558 ns synp~reg0 2 REG LC_X78_Y1_N4 1 " "Info: 2: + IC(4.684 ns) + CELL(0.562 ns) = 6.558 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "5.246 ns" { syndin synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.874 ns 28.58 % " "Info: Total cell delay = 1.874 ns ( 28.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.684 ns 71.42 % " "Info: Total interconnect delay = 4.684 ns ( 71.42 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "6.558 ns" { syndin synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.558 ns" { syndin syndin~out0 synp~reg0 } { 0.000ns 0.000ns 4.684ns } { 0.000ns 1.312ns 0.562ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.660 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 2 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { clk } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.141 ns) + CELL(0.644 ns) 3.660 ns synp~reg0 2 REG LC_X78_Y1_N4 1 " "Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "2.785 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.50 % " "Info: Total cell delay = 1.519 ns ( 41.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.141 ns 58.50 % " "Info: Total interconnect delay = 2.141 ns ( 58.50 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "6.558 ns" { syndin synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.558 ns" { syndin syndin~out0 synp~reg0 } { 0.000ns 0.000ns 4.684ns } { 0.000ns 1.312ns 0.562ns } } } { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk synp synp~reg0 7.392 ns register " "Info: tco from clock \"clk\" to destination pin \"synp\" through register \"synp~reg0\" is 7.392 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.660 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 2 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { clk } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.141 ns) + CELL(0.644 ns) 3.660 ns synp~reg0 2 REG LC_X78_Y1_N4 1 " "Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "2.785 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.50 % " "Info: Total cell delay = 1.519 ns ( 41.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.141 ns 58.50 % " "Info: Total interconnect delay = 2.141 ns ( 58.50 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns + " "Info: + Micro clock to output delay of source is 0.202 ns" {  } { { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.530 ns + Longest register pin " "Info: + Longest register to pin delay is 3.530 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns synp~reg0 1 REG LC_X78_Y1_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(2.495 ns) 3.530 ns synp 2 PIN PIN_AC24 0 " "Info: 2: + IC(1.035 ns) + CELL(2.495 ns) = 3.530 ns; Loc. = PIN_AC24; Fanout = 0; PIN Node = 'synp'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.530 ns" { synp~reg0 synp } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.495 ns 70.68 % " "Info: Total cell delay = 2.495 ns ( 70.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.035 ns 29.32 % " "Info: Total interconnect delay = 1.035 ns ( 29.32 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.530 ns" { synp~reg0 synp } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.530 ns" { synp~reg0 synp } { 0.000ns 1.035ns } { 0.000ns 2.495ns } } }  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.530 ns" { synp~reg0 synp } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.530 ns" { synp~reg0 synp } { 0.000ns 1.035ns } { 0.000ns 2.495ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "synp~reg0 enab clk -2.007 ns register " "Info: th for register \"synp~reg0\" (data pin = \"enab\", clock pin = \"clk\") is -2.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.660 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 2 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { clk } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.141 ns) + CELL(0.644 ns) 3.660 ns synp~reg0 2 REG LC_X78_Y1_N4 1 " "Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "2.785 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.50 % " "Info: Total cell delay = 1.519 ns ( 41.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.141 ns 58.50 % " "Info: Total interconnect delay = 2.141 ns ( 58.50 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.114 ns + " "Info: + Micro hold delay of destination is 0.114 ns" {  } { { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.781 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.490 ns) 1.490 ns enab 1 PIN PIN_AD25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.490 ns) = 1.490 ns; Loc. = PIN_AD25; Fanout = 1; PIN Node = 'enab'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { enab } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.021 ns) + CELL(0.270 ns) 5.781 ns synp~reg0 2 REG LC_X78_Y1_N4 1 " "Info: 2: + IC(4.021 ns) + CELL(0.270 ns) = 5.781 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "4.291 ns" { enab synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.760 ns 30.44 % " "Info: Total cell delay = 1.760 ns ( 30.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.021 ns 69.56 % " "Info: Total interconnect delay = 4.021 ns ( 69.56 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "5.781 ns" { enab synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.781 ns" { enab enab~out0 synp~reg0 } { 0.000ns 0.000ns 4.021ns } { 0.000ns 1.490ns 0.270ns } } }  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "5.781 ns" { enab synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.781 ns" { enab enab~out0 synp~reg0 } { 0.000ns 0.000ns 4.021ns } { 0.000ns 1.490ns 0.270ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 15:03:33 2005 " "Info: Processing ended: Mon Dec 26 15:03:33 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
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