synp.tan.qmsg

三端口输入

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 15:03:32 2005 " "Info: Processing started: Mon Dec 26 15:03:32 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off synp -c synp --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off synp -c synp --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register syndin1 synp~reg0 390.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 390.02 MHz between source register \"syndin1\" and destination register \"synp~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.564 ns " "Info: fmax restricted to clock pin edge rate 2.564 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.167 ns + Longest register register " "Info: + Longest register to register delay is 1.167 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns syndin1 1 REG LC_X78_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y1_N2; Fanout = 1; REG Node = 'syndin1'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { syndin1 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.497 ns) + CELL(0.670 ns) 1.167 ns synp~reg0 2 REG LC_X78_Y1_N4 1 " "Info: 2: + IC(0.497 ns) + CELL(0.670 ns) = 1.167 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "1.167 ns" { syndin1 synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.670 ns 57.41 % " "Info: Total cell delay = 0.670 ns ( 57.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.497 ns 42.59 % " "Info: Total interconnect delay = 0.497 ns ( 42.59 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "1.167 ns" { syndin1 synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.167 ns" { syndin1 synp~reg0 } { 0.000ns 0.497ns } { 0.000ns 0.670ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.660 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 2 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { clk } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.141 ns) + CELL(0.644 ns) 3.660 ns synp~reg0 2 REG LC_X78_Y1_N4 1 " "Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N4; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "2.785 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.50 % " "Info: Total cell delay = 1.519 ns ( 41.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.141 ns 58.50 % " "Info: Total interconnect delay = 2.141 ns ( 58.50 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.660 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 2 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 2; CLK Node = 'clk'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { clk } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.141 ns) + CELL(0.644 ns) 3.660 ns syndin1 2 REG LC_X78_Y1_N2 1 " "Info: 2: + IC(2.141 ns) + CELL(0.644 ns) = 3.660 ns; Loc. = LC_X78_Y1_N2; Fanout = 1; REG Node = 'syndin1'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "2.785 ns" { clk syndin1 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.50 % " "Info: Total cell delay = 1.519 ns ( 41.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.141 ns 58.50 % " "Info: Total interconnect delay = 2.141 ns ( 58.50 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk syndin1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 syndin1 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk syndin1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 syndin1 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns + " "Info: + Micro clock to output delay of source is 0.202 ns" {  } { { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "1.167 ns" { syndin1 synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.167 ns" { syndin1 synp~reg0 } { 0.000ns 0.497ns } { 0.000ns 0.670ns } } } { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 synp~reg0 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "3.660 ns" { clk syndin1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.660 ns" { clk clk~out0 syndin1 } { 0.000ns 0.000ns 2.141ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { synp~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { synp~reg0 } {  } {  } } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0}