synp.fit.qmsg

三端口输入

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 3.30 2 1 0 " "Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 2 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 61 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  61 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 59 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  59 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 54 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  54 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 55 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  55 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 1 58 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  58 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 61 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  61 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 57 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  57 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 54 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  54 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.808 ns register register " "Info: Estimated most critical path is register to register delay of 0.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns syndin1 1 REG LAB_X78_Y1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X78_Y1; Fanout = 1; REG Node = 'syndin1'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "" { syndin1 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.138 ns) + CELL(0.670 ns) 0.808 ns synp~reg0 2 REG LAB_X78_Y1 1 " "Info: 2: + IC(0.138 ns) + CELL(0.670 ns) = 0.808 ns; Loc. = LAB_X78_Y1; Fanout = 1; REG Node = 'synp~reg0'" {  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "0.808 ns" { syndin1 synp~reg0 } "NODE_NAME" } "" } } { "synp.vhd" "" { Text "C:/altera/project/experiment/maichong/synp.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.670 ns 82.92 % " "Info: Total cell delay = 0.670 ns ( 82.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.138 ns 17.08 % " "Info: Total interconnect delay = 0.138 ns ( 17.08 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" "" { Report "C:/altera/project/experiment/maichong/db/synp_cmp.qrpt" Compiler "synp" "UNKNOWN" "V1" "C:/altera/project/experiment/maichong/db/synp.quartus_db" { Floorplan "C:/altera/project/experiment/maichong/" "" "0.808 ns" { syndin1 synp~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 15:03:20 2005 " "Info: Processing ended: Mon Dec 26 15:03:20 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0}  } {  } 0}