📄 synp.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L6Q is synp~reg0
--operation mode is normal
A1L6Q_lut_out = syndin1 & (!enab & !syndin) # !syndin1 & (enab & syndin);
A1L6Q = DFFEAS(A1L6Q_lut_out, clk, VCC, , , , , , );
--syndin1 is syndin1
--operation mode is normal
syndin1_lut_out = syndin;
syndin1 = DFFEAS(syndin1_lut_out, clk, VCC, , , , , , );
--enab is enab
--operation mode is input
enab = INPUT();
--syndin is syndin
--operation mode is input
syndin = INPUT();
--clk is clk
--operation mode is input
clk = INPUT();
--synp is synp
--operation mode is output
synp = OUTPUT(A1L6Q);
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