synp.vhd

来自「三端口输入」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity synp is
	port(clk: in std_logic;
		enab: in std_logic;
	   	syndin: in std_logic;
		 synp: out std_logic);
end synp;

architecture xsynp of synp is 
signal syndin1 : std_logic;
begin

process(clk)
begin
if clk'event and clk='1' then
	syndin1<=syndin;
	if ( syndin=enab and syndin1=not enab) then
		synp<='1';
	else
		synp<='0';
	end if;
end if;
end process;

end xsynp;