mc9s12dp256.lst

Freescale HCS12DP256 CAN通讯程序源代码

  265:  volatile CAN4IDAR7STR _CAN4IDAR7;                          /* MSCAN4 Identifier Acceptance Register 7 */
  266:  volatile CAN4IDMR0STR _CAN4IDMR0;                          /* MSCAN4 Identifier Mask Register 0 */
  267:  volatile CAN4IDMR1STR _CAN4IDMR1;                          /* MSCAN4 Identifier Mask Register 1 */
  268:  volatile CAN4IDMR2STR _CAN4IDMR2;                          /* MSCAN4 Identifier Mask Register 2 */
  269:  volatile CAN4IDMR3STR _CAN4IDMR3;                          /* MSCAN4 Identifier Mask Register 3 */
  270:  volatile CAN4IDMR4STR _CAN4IDMR4;                          /* MSCAN4 Identifier Mask Register 4 */
  271:  volatile CAN4IDMR5STR _CAN4IDMR5;                          /* MSCAN4 Identifier Mask Register 5 */
  272:  volatile CAN4IDMR6STR _CAN4IDMR6;                          /* MSCAN4 Identifier Mask Register 6 */
  273:  volatile CAN4IDMR7STR _CAN4IDMR7;                          /* MSCAN4 Identifier Mask Register 7 */
  274:  volatile CAN4RFLGSTR _CAN4RFLG;                            /* MSCAN4 Receiver Flag Register */
  275:  volatile CAN4RIERSTR _CAN4RIER;                            /* MSCAN4 Receiver Interrupt Enable Register */
  276:  volatile CAN4RXDLRSTR _CAN4RXDLR;                          /* MSCAN4 Receive Data Length Register */
  277:  volatile CAN4RXDSR0STR _CAN4RXDSR0;                        /* MSCAN4 Receive Data Segment Register 0 */
  278:  volatile CAN4RXDSR1STR _CAN4RXDSR1;                        /* MSCAN4 Receive Data Segment Register 1 */
  279:  volatile CAN4RXDSR2STR _CAN4RXDSR2;                        /* MSCAN4 Receive Data Segment Register 2 */
  280:  volatile CAN4RXDSR3STR _CAN4RXDSR3;                        /* MSCAN4 Receive Data Segment Register 3 */
  281:  volatile CAN4RXDSR4STR _CAN4RXDSR4;                        /* MSCAN4 Receive Data Segment Register 4 */
  282:  volatile CAN4RXDSR5STR _CAN4RXDSR5;                        /* MSCAN4 Receive Data Segment Register 5 */
  283:  volatile CAN4RXDSR6STR _CAN4RXDSR6;                        /* MSCAN4 Receive Data Segment Register 6 */
  284:  volatile CAN4RXDSR7STR _CAN4RXDSR7;                        /* MSCAN4 Receive Data Segment Register 7 */
  285:  volatile CAN4RXERRSTR _CAN4RXERR;                          /* MSCAN4 Receive Error Counter Register */
  286:  volatile CAN4RXIDR0STR _CAN4RXIDR0;                        /* MSCAN4 Receive Identifier Register 0 */
  287:  volatile CAN4RXIDR1STR _CAN4RXIDR1;                        /* MSCAN4 Receive Identifier Register 1 */
  288:  volatile CAN4RXIDR2STR _CAN4RXIDR2;                        /* MSCAN4 Receive Identifier Register 2 */
  289:  volatile CAN4RXIDR3STR _CAN4RXIDR3;                        /* MSCAN4 Receive Identifier Register 3 */
  290:  volatile CAN4TAAKSTR _CAN4TAAK;                            /* MSCAN4 Transmitter Message Abort Control */
  291:  volatile CAN4TARQSTR _CAN4TARQ;                            /* MSCAN 4 Transmitter Message Abort Request */
  292:  volatile CAN4TBSELSTR _CAN4TBSEL;                          /* MSCAN4 Transmit Buffer Selection */
  293:  volatile CAN4TFLGSTR _CAN4TFLG;                            /* MSCAN4 Transmitter Flag Register */
  294:  volatile CAN4TIERSTR _CAN4TIER;                            /* MSCAN4 Transmitter Interrupt Enable Register */
  295:  volatile CAN4TXDLRSTR _CAN4TXDLR;                          /* MSCAN4 Transmit Data Length Register */
  296:  volatile CAN4TXDSR0STR _CAN4TXDSR0;                        /* MSCAN4 Transmit Data Segment Register 0 */
  297:  volatile CAN4TXDSR1STR _CAN4TXDSR1;                        /* MSCAN4 Transmit Data Segment Register 1 */
  298:  volatile CAN4TXDSR2STR _CAN4TXDSR2;                        /* MSCAN4 Transmit Data Segment Register 2 */
  299:  volatile CAN4TXDSR3STR _CAN4TXDSR3;                        /* MSCAN4 Transmit Data Segment Register 3 */
  300:  volatile CAN4TXDSR4STR _CAN4TXDSR4;                        /* MSCAN4 Transmit Data Segment Register 4 */
  301:  volatile CAN4TXDSR5STR _CAN4TXDSR5;                        /* MSCAN4 Transmit Data Segment Register 5 */
  302:  volatile CAN4TXDSR6STR _CAN4TXDSR6;                        /* MSCAN4 Transmit Data Segment Register 6 */
  303:  volatile CAN4TXDSR7STR _CAN4TXDSR7;                        /* MSCAN4 Transmit Data Segment Register 7 */
  304:  volatile CAN4TXERRSTR _CAN4TXERR;                          /* MSCAN4 Transmit Error Counter Register */
  305:  volatile CAN4TXIDR0STR _CAN4TXIDR0;                        /* MSCAN4 Transmit Identifier Register 0 */
  306:  volatile CAN4TXIDR1STR _CAN4TXIDR1;                        /* MSCAN4 Transmit Identifier Register 1 */
  307:  volatile CAN4TXIDR2STR _CAN4TXIDR2;                        /* MSCAN4 Transmit Identifier Register 2 */
  308:  volatile CAN4TXIDR3STR _CAN4TXIDR3;                        /* MSCAN4 Transmit Identifier Register 3 */
  309:  volatile CAN4TXTBPRSTR _CAN4TXTBPR;                        /* MSCAN4 Transmit Transmit Buffer Priority */
  310:  volatile CFORCSTR _CFORC;                                  /* Timer Compare Force Register */
  311:  volatile CLKSELSTR _CLKSEL;                                /* CRG Clock Select Register */
  312:  volatile COPCTLSTR _COPCTL;                                /* CRG COP Control Register */
  313:  volatile CRGFLGSTR _CRGFLG;                                /* CRG Flags Register */
  314:  volatile CRGINTSTR _CRGINT;                                /* CRG Interrupt Enable Register */
  315:  volatile DDRESTR _DDRE;                                    /* Port E Data Direction Register */
  316:  volatile DDRHSTR _DDRH;                                    /* Port H Data Direction Register */
  317:  volatile DDRJSTR _DDRJ;                                    /* Port J Data Direction Register */
  318:  volatile DDRKSTR _DDRK;                                    /* Port K Data Direction Register */
  319:  volatile DDRMSTR _DDRM;                                    /* Port M Data Direction Register */
  320:  volatile DDRPSTR _DDRP;                                    /* Port P Data Direction Register */
  321:  volatile DDRSSTR _DDRS;                                    /* Port S Data Direction Register */
  322:  volatile DDRTSTR _DDRT;                                    /* Port T Data Direction Register */
  323:  volatile DLCBARDSTR _DLCBARD;                              /* BDLC Analog Round Trip Delay Register */
  324:  volatile DLCBCR1STR _DLCBCR1;                              /* BDLC Control Register 1 */
  325:  volatile DLCBCR2STR _DLCBCR2;                              /* BDLC Control Register 2 */
  326:  volatile DLCBDRSTR _DLCBDR;                                /* BDLC Data Register */
  327:  volatile DLCBRSRSTR _DLCBRSR;                              /* BDLC Rate Select Register */
  328:  volatile DLCBSVRSTR _DLCBSVR;                              /* BDLC State Vector Register */
  329:  volatile DLCSCRSTR _DLCSCR;                                /* BDLC Control Register */
  330:  volatile DLYCTSTR _DLYCT;                                  /* Delay Counter Control Register */
  331:  volatile EBICTLSTR _EBICTL;                                /* External Bus Interface Control */
  332:  volatile ECLKDIVSTR _ECLKDIV;                              /* EEPROM Clock Divider Register */
  333:  volatile ECMDSTR _ECMD;                                    /* EEPROM Command Buffer and Register */
  334:  volatile ECNFGSTR _ECNFG;                                  /* EEPROM Configuration Register */
  335:  volatile EPROTSTR _EPROT;                                  /* EEPROM Protection Register */
  336:  volatile ESTATSTR _ESTAT;                                  /* EEPROM Status Register */
  337:  volatile FCLKDIVSTR _FCLKDIV;                              /* Flash Clock Divider Register */
  338:  volatile FCMDSTR _FCMD;                                    /* Flash Command Buffer and Register */
  339:  volatile FCNFGSTR _FCNFG;                                  /* Flash Configuration Register */
  340:  volatile FPROTSTR _FPROT;                                  /* Flash Protection Register */
  341:  volatile FSECSTR _FSEC;                                    /* Flash Security Register */
  342:  volatile FSTATSTR _FSTAT;                                  /* Flash Status Register */
  343:  volatile HPRIOSTR _HPRIO;                                  /* Highest Priority I Interrupt */
  344:  volatile IBADSTR _IBAD;                                    /* IIC Address Register */
  345:  volatile IBCRSTR _IBCR;                                    /* IIC Control Register */
  346:  volatile IBDRSTR _IBDR;                                    /* IIC Data I/O Register */
  347:  volatile IBFDSTR _IBFD;                                    /* IIC Frequency Divider Register */
  348:  volatile IBSRSTR _IBSR;                                    /* IIC Status Register */
  349:  volatile ICOVWSTR _ICOVW;                                  /* Input Control Overwrite Register */
  350:  volatile ICPARSTR _ICPAR;                                  /* Input Control Pulse Accumulator Register */
  351:  volatile ICSYSSTR _ICSYS;                                  /* Input Control System Control Register */
  352:  volatile INITEESTR _INITEE;                                /* Initialization of Internal EEPROM Position Register */
  353:  volatile INITRGSTR _INITRG;                                /* Initialization of Internal Register Position Register */
  354:  volatile INITRMSTR _INITRM;                                /* Initialization of Internal RAM Position Register */
  355:  volatile INTCRSTR _INTCR;                                  /* Interrupt Control Register */
  356:  volatile ITCRSTR _ITCR;                                    /* Interrupt Test Control Register */
  357:  volatile ITESTSTR _ITEST;                                  /* Interrupt Test Register */
  358:  volatile MCCTLSTR _MCCTL;                                  /* Modulus Down Counter underflow */
  359:  volatile MCFLGSTR _MCFLG;                                  /* 16-Bit Modulus Down Counter Flag Register */
  360:  volatile MEMSIZ0STR _MEMSIZ0;                              /* Memory Size Register Zero */
  361:  volatile MEMSIZ1STR _MEMSIZ1;                              /* Memory Size Register One */
  362:  volatile MISCSTR _MISC;                                    /* Miscellaneous Mapping Control Register */
  363:  volatile MODESTR _MODE;                                    /* Mode Register */
  364:  volatile MODRRSTR _MODRR;                                  /* Module Routing Register */
  365:  volatile MTST0STR _MTST0;                                  /* MTST0 */
  366:  volatile MTST1STR _MTST1;                                  /* MTST1 */
  367:  volatile OC7DSTR _OC7D;                                    /* Output Compare 7 Data Register */
  368:  volatile OC7MSTR _OC7M;                                    /* Output Compare 7 Mask Register */
  369:  volatile PACTLSTR _PACTL;                                  /* 16-Bit Pulse Accumulator A Control Register */
  370:  volatile PAFLGSTR _PAFLG;                                  /* Pulse Accumulator A Flag Register */
  371:  volatile PARTIDHSTR _PARTIDH;                              /* Part ID Register High */
  372:  volatile PARTIDLSTR _PARTIDL;                              /* Part ID Register Low */
  373:  volatile PBCTLSTR _PBCTL;                                  /* 16-Bit Pulse Accumulator B Control Register */
  374:  volatile PBFLGSTR _PBFLG;                                  /* Pulse Accumulator B Flag Register */
  375:  volatile PEARSTR _PEAR;                                    /* Port E Assignment Register */
  376:  volatile PERHSTR _PERH;                                    /* Port H Pull Device Enable Register */
  377:  volatile PERJSTR _PERJ;                                    /* Port J Pull Device Enable Register */
  378:  volatile PERMSTR _PERM;                                    /* Port M Pull Device Enable Register */
  379:  volatile PERPSTR _PERP;                                    /* Port P Pull Device Enable Register */
  380:  volatile PERSSTR _PERS;                                    /* Port S Pull Device Enable Register */
  381:  volatile PERTSTR _PERT;                                    /* Port T Pull Device Enable Register */
  382:  volatile PIEHSTR _PIEH;                                    /* Port H Interrupt Enable Register */
  383:  volatile PIEJSTR _PIEJ;                                    /* Port J Interrupt Enable Register */
  384:  volatile PIEPSTR _PIEP;                                    /* Port P Interrupt Enable Register */
  385:  volatile PIFHSTR _PIFH;                                    /* Port H Interrupt Flag Register */
  386:  volatile PIFJSTR _PIFJ;                                    /* Port J Interrupt Flag Register */
  387:  volatile PIFPSTR _PIFP;                                    /* Port P Interrupt Flag Register */
  388:  volatile PLLCTLSTR _PLLCTL;                                /* CRG PLL Control Register */
  389:  volatile PORTAD0STR _PORTAD0;                              /* Port AD0 Register */
  390:  volatile PORTAD1STR _PORTAD1;                              /* Port AD1 Register */
  391:  volatile PORTESTR _PORTE;                                  /* Port E Register */
  392:  volatile PORTKSTR _PORTK;                                  /* Port K Data Register */
  393:  volatile PPAGESTR _PPAGE;                                  /* Page Index Register */
  394:  volatile PPSHSTR _PPSH;                                    /* Port H Polarity Select Register */
  395:  volatile PPSJSTR _PPSJ;                                    /* PortJP Polarity Select Register */
  396:  volatile PPSMSTR _PPSM;                                    /* Port M Polarity Select Register */
  397:  volatile PPSPSTR _PPSP;                                    /* Port P Polarity Select Register */