mc9s12dp256.lst

Freescale HCS12DP256 CAN通讯程序源代码

ANSI-C/cC++ Compiler for HC12 V-5.0.24 Build 4047, Feb 17 2004

    1:  /* Based on CPU DB MC9S12DP256, version 2.87.292 (RegistersPrg V1.052) */
    2:  /* DataSheet : 9S12DP256BDGV2/D V02.14 */
    3:  
    4:  #include <MC9S12DP256.h>
    5:  
    6:  
    7:  volatile ARMCOPSTR _ARMCOP;                                /* CRG COP Timer Arm/Reset Register */
    8:  volatile ATD0DIENSTR _ATD0DIEN;                            /* ATD 0 Input Enable Mask Register */
    9:  volatile ATD0STAT0STR _ATD0STAT0;                          /* ATD 0 Status Register 0 */
   10:  volatile ATD0STAT1STR _ATD0STAT1;                          /* ATD 0 Status Register 1 */
   11:  volatile ATD1DIENSTR _ATD1DIEN;                            /* ATD 1 Input Enable Mask Register */
   12:  volatile ATD1STAT0STR _ATD1STAT0;                          /* ATD 1 Status Register 0 */
   13:  volatile ATD1STAT1STR _ATD1STAT1;                          /* ATD 1 Status Register 1 */
   14:  volatile BDMCCRSTR _BDMCCR;                                /* BDM CCR Holding Register */
   15:  volatile BDMINRSTR _BDMINR;                                /* BDM Internal Register Position Register */
   16:  volatile BDMSTSSTR _BDMSTS;                                /* BDM Status Register */
   17:  volatile BKP0HSTR _BKP0H;                                  /* First Address High Byte Breakpoint Register */
   18:  volatile BKP0LSTR _BKP0L;                                  /* First Address Low Byte Breakpoint Register */
   19:  volatile BKP0XSTR _BKP0X;                                  /* First Address Memory Expansion Breakpoint Register */
   20:  volatile BKP1HSTR _BKP1H;                                  /* Data (Second Address) High Byte Breakpoint Register */
   21:  volatile BKP1LSTR _BKP1L;                                  /* Data (Second Address) Low Byte Breakpoint Register */
   22:  volatile BKP1XSTR _BKP1X;                                  /* Second Address Memory Expansion Breakpoint Register */
   23:  volatile BKPCT0STR _BKPCT0;                                /* Breakpoint Control Register 0 */
   24:  volatile BKPCT1STR _BKPCT1;                                /* Breakpoint Control Register 1 */
   25:  volatile CAN0BTR0STR _CAN0BTR0;                            /* MSCAN 0 Bus Timing Register 0 */
   26:  volatile CAN0BTR1STR _CAN0BTR1;                            /* MSCAN 0 Bus Timing Register 1 */
   27:  volatile CAN0CTL0STR _CAN0CTL0;                            /* MSCAN 0 Control 0 Register */
   28:  volatile CAN0CTL1STR _CAN0CTL1;                            /* MSCAN 0 Control 1 Register */
   29:  volatile CAN0IDACSTR _CAN0IDAC;                            /* MSCAN 0 Identifier Acceptance Control Register */
   30:  volatile CAN0IDAR0STR _CAN0IDAR0;                          /* MSCAN 0 Identifier Acceptance Register 0 */
   31:  volatile CAN0IDAR1STR _CAN0IDAR1;                          /* MSCAN 0 Identifier Acceptance Register 1 */
   32:  volatile CAN0IDAR2STR _CAN0IDAR2;                          /* MSCAN 0 Identifier Acceptance Register 2 */
   33:  volatile CAN0IDAR3STR _CAN0IDAR3;                          /* MSCAN 0 Identifier Acceptance Register 3 */
   34:  volatile CAN0IDAR4STR _CAN0IDAR4;                          /* MSCAN 0 Identifier Acceptance Register 4 */
   35:  volatile CAN0IDAR5STR _CAN0IDAR5;                          /* MSCAN 0 Identifier Acceptance Register 5 */
   36:  volatile CAN0IDAR6STR _CAN0IDAR6;                          /* MSCAN 0 Identifier Acceptance Register 6 */
   37:  volatile CAN0IDAR7STR _CAN0IDAR7;                          /* MSCAN 0 Identifier Acceptance Register 7 */
   38:  volatile CAN0IDMR0STR _CAN0IDMR0;                          /* MSCAN 0 Identifier Mask Register 0 */
   39:  volatile CAN0IDMR1STR _CAN0IDMR1;                          /* MSCAN 0 Identifier Mask Register 1 */
   40:  volatile CAN0IDMR2STR _CAN0IDMR2;                          /* MSCAN 0 Identifier Mask Register 2 */
   41:  volatile CAN0IDMR3STR _CAN0IDMR3;                          /* MSCAN 0 Identifier Mask Register 3 */
   42:  volatile CAN0IDMR4STR _CAN0IDMR4;                          /* MSCAN 0 Identifier Mask Register 4 */
   43:  volatile CAN0IDMR5STR _CAN0IDMR5;                          /* MSCAN 0 Identifier Mask Register 5 */
   44:  volatile CAN0IDMR6STR _CAN0IDMR6;                          /* MSCAN 0 Identifier Mask Register 6 */
   45:  volatile CAN0IDMR7STR _CAN0IDMR7;                          /* MSCAN 0 Identifier Mask Register 7 */
   46:  volatile CAN0RFLGSTR _CAN0RFLG;                            /* MSCAN 0 Receiver Flag Register */
   47:  volatile CAN0RIERSTR _CAN0RIER;                            /* MSCAN 0 Receiver Interrupt Enable Register */
   48:  volatile CAN0RXDLRSTR _CAN0RXDLR;                          /* MSCAN 0 Receive Data Length Register */
   49:  volatile CAN0RXDSR0STR _CAN0RXDSR0;                        /* MSCAN 0 Receive Data Segment Register 0 */
   50:  volatile CAN0RXDSR1STR _CAN0RXDSR1;                        /* MSCAN 0 Receive Data Segment Register 1 */
   51:  volatile CAN0RXDSR2STR _CAN0RXDSR2;                        /* MSCAN 0 Receive Data Segment Register 2 */
   52:  volatile CAN0RXDSR3STR _CAN0RXDSR3;                        /* MSCAN 0 Receive Data Segment Register 3 */
   53:  volatile CAN0RXDSR4STR _CAN0RXDSR4;                        /* MSCAN 0 Receive Data Segment Register 4 */
   54:  volatile CAN0RXDSR5STR _CAN0RXDSR5;                        /* MSCAN 0 Receive Data Segment Register 5 */
   55:  volatile CAN0RXDSR6STR _CAN0RXDSR6;                        /* MSCAN 0 Receive Data Segment Register 6 */
   56:  volatile CAN0RXDSR7STR _CAN0RXDSR7;                        /* MSCAN 0 Receive Data Segment Register 7 */
   57:  volatile CAN0RXERRSTR _CAN0RXERR;                          /* MSCAN 0 Receive Error Counter Register */
   58:  volatile CAN0RXIDR0STR _CAN0RXIDR0;                        /* MSCAN 0 Receive Identifier Register 0 */
   59:  volatile CAN0RXIDR1STR _CAN0RXIDR1;                        /* MSCAN 0 Receive Identifier Register 1 */
   60:  volatile CAN0RXIDR2STR _CAN0RXIDR2;                        /* MSCAN 0 Receive Identifier Register 2 */
   61:  volatile CAN0RXIDR3STR _CAN0RXIDR3;                        /* MSCAN 0 Receive Identifier Register 3 */
   62:  volatile CAN0TAAKSTR _CAN0TAAK;                            /* MSCAN 0 Transmitter Message Abort Control */
   63:  volatile CAN0TARQSTR _CAN0TARQ;                            /* MSCAN 0 Transmitter Message Abort Request */
   64:  volatile CAN0TBSELSTR _CAN0TBSEL;                          /* MSCAN 0 Transmit Buffer Selection */
   65:  volatile CAN0TFLGSTR _CAN0TFLG;                            /* MSCAN 0 Transmitter Flag Register */
   66:  volatile CAN0TIERSTR _CAN0TIER;                            /* MSCAN 0 Transmitter Interrupt Enable Register */
   67:  volatile CAN0TXDLRSTR _CAN0TXDLR;                          /* MSCAN 0 Transmit Data Length Register */
   68:  volatile CAN0TXDSR0STR _CAN0TXDSR0;                        /* MSCAN 0 Transmit Data Segment Register 0 */
   69:  volatile CAN0TXDSR1STR _CAN0TXDSR1;                        /* MSCAN 0 Transmit Data Segment Register 1 */
   70:  volatile CAN0TXDSR2STR _CAN0TXDSR2;                        /* MSCAN 0 Transmit Data Segment Register 2 */
   71:  volatile CAN0TXDSR3STR _CAN0TXDSR3;                        /* MSCAN 0 Transmit Data Segment Register 3 */
   72:  volatile CAN0TXDSR4STR _CAN0TXDSR4;                        /* MSCAN 0 Transmit Data Segment Register 4 */
   73:  volatile CAN0TXDSR5STR _CAN0TXDSR5;                        /* MSCAN 0 Transmit Data Segment Register 5 */
   74:  volatile CAN0TXDSR6STR _CAN0TXDSR6;                        /* MSCAN 0 Transmit Data Segment Register 6 */
   75:  volatile CAN0TXDSR7STR _CAN0TXDSR7;                        /* MSCAN 0 Transmit Data Segment Register 7 */
   76:  volatile CAN0TXERRSTR _CAN0TXERR;                          /* MSCAN 0 Transmit Error Counter Register */
   77:  volatile CAN0TXIDR0STR _CAN0TXIDR0;                        /* MSCAN 0 Transmit Identifier Register 0 */
   78:  volatile CAN0TXIDR1STR _CAN0TXIDR1;                        /* MSCAN 0 Transmit Identifier Register 1 */
   79:  volatile CAN0TXIDR2STR _CAN0TXIDR2;                        /* MSCAN 0 Transmit Identifier Register 2 */
   80:  volatile CAN0TXIDR3STR _CAN0TXIDR3;                        /* MSCAN 0 Transmit Identifier Register 3 */
   81:  volatile CAN0TXTBPRSTR _CAN0TXTBPR;                        /* MSCAN 0 Transmit Buffer Priority */
   82:  volatile CAN1BTR0STR _CAN1BTR0;                            /* MSCAN 1 Bus Timing Register 0 */
   83:  volatile CAN1BTR1STR _CAN1BTR1;                            /* MSCAN 1 Bus Timing Register 1 */
   84:  volatile CAN1CTL0STR _CAN1CTL0;                            /* MSCAN 1 Control 0 Register */
   85:  volatile CAN1CTL1STR _CAN1CTL1;                            /* MSCAN 1 Control 1 Register */
   86:  volatile CAN1IDACSTR _CAN1IDAC;                            /* MSCAN 1 Identifier Acceptance Control Register */
   87:  volatile CAN1IDAR0STR _CAN1IDAR0;                          /* MSCAN 1 Identifier Acceptance Register 0 */
   88:  volatile CAN1IDAR1STR _CAN1IDAR1;                          /* MSCAN 1 Identifier Acceptance Register 1 */
   89:  volatile CAN1IDAR2STR _CAN1IDAR2;                          /* MSCAN 1 Identifier Acceptance Register 2 */
   90:  volatile CAN1IDAR3STR _CAN1IDAR3;                          /* MSCAN 1 Identifier Acceptance Register 3 */
   91:  volatile CAN1IDAR4STR _CAN1IDAR4;                          /* MSCAN 1 Identifier Acceptance Register 4 */
   92:  volatile CAN1IDAR5STR _CAN1IDAR5;                          /* MSCAN 1 Identifier Acceptance Register 5 */
   93:  volatile CAN1IDAR6STR _CAN1IDAR6;                          /* MSCAN 1 Identifier Acceptance Register 6 */
   94:  volatile CAN1IDAR7STR _CAN1IDAR7;                          /* MSCAN 1 Identifier Acceptance Register 7 */
   95:  volatile CAN1IDMR0STR _CAN1IDMR0;                          /* MSCAN 1 Identifier Mask Register 0 */
   96:  volatile CAN1IDMR1STR _CAN1IDMR1;                          /* MSCAN 1 Identifier Mask Register 1 */
   97:  volatile CAN1IDMR2STR _CAN1IDMR2;                          /* MSCAN 1 Identifier Mask Register 2 */
   98:  volatile CAN1IDMR3STR _CAN1IDMR3;                          /* MSCAN 1 Identifier Mask Register 3 */
   99:  volatile CAN1IDMR4STR _CAN1IDMR4;                          /* MSCAN 1 Identifier Mask Register 4 */
  100:  volatile CAN1IDMR5STR _CAN1IDMR5;                          /* MSCAN 1 Identifier Mask Register 5 */
  101:  volatile CAN1IDMR6STR _CAN1IDMR6;                          /* MSCAN 1 Identifier Mask Register 6 */
  102:  volatile CAN1IDMR7STR _CAN1IDMR7;                          /* MSCAN 1 Identifier Mask Register 7 */
  103:  volatile CAN1RFLGSTR _CAN1RFLG;                            /* MSCAN 1 Receiver Flag Register */
  104:  volatile CAN1RIERSTR _CAN1RIER;                            /* MSCAN 1 Receiver Interrupt Enable Register */
  105:  volatile CAN1RXDLRSTR _CAN1RXDLR;                          /* MSCAN 1 Receive Data Length Register */
  106:  volatile CAN1RXDSR0STR _CAN1RXDSR0;                        /* MSCAN 1 Receive Data Segment Register 0 */
  107:  volatile CAN1RXDSR1STR _CAN1RXDSR1;                        /* MSCAN 1 Receive Data Segment Register 1 */
  108:  volatile CAN1RXDSR2STR _CAN1RXDSR2;                        /* MSCAN 1 Receive Data Segment Register 2 */
  109:  volatile CAN1RXDSR3STR _CAN1RXDSR3;                        /* MSCAN 1 Receive Data Segment Register 3 */
  110:  volatile CAN1RXDSR4STR _CAN1RXDSR4;                        /* MSCAN 1 Receive Data Segment Register 4 */
  111:  volatile CAN1RXDSR5STR _CAN1RXDSR5;                        /* MSCAN 1 Receive Data Segment Register 5 */
  112:  volatile CAN1RXDSR6STR _CAN1RXDSR6;                        /* MSCAN 1 Receive Data Segment Register 6 */
  113:  volatile CAN1RXDSR7STR _CAN1RXDSR7;                        /* MSCAN 1 Receive Data Segment Register 7 */
  114:  volatile CAN1RXERRSTR _CAN1RXERR;                          /* MSCAN 1 Receive Error Counter Register */
  115:  volatile CAN1RXIDR0STR _CAN1RXIDR0;                        /* MSCAN 1 Receive Identifier Register 0 */
  116:  volatile CAN1RXIDR1STR _CAN1RXIDR1;                        /* MSCAN 1 Receive Identifier Register 1 */
  117:  volatile CAN1RXIDR2STR _CAN1RXIDR2;                        /* MSCAN 1 Receive Identifier Register 2 */
  118:  volatile CAN1RXIDR3STR _CAN1RXIDR3;                        /* MSCAN 1 Receive Identifier Register 3 */
  119:  volatile CAN1TAAKSTR _CAN1TAAK;                            /* MSCAN 1 Transmitter Message Abort Control */
  120:  volatile CAN1TARQSTR _CAN1TARQ;                            /* MSCAN 1 Transmitter Message Abort Request */
  121:  volatile CAN1TBSELSTR _CAN1TBSEL;                          /* MSCAN 1 Transmit Buffer Selection */
  122:  volatile CAN1TFLGSTR _CAN1TFLG;                            /* MSCAN 1 Transmitter Flag Register */
  123:  volatile CAN1TIERSTR _CAN1TIER;                            /* MSCAN 1 Transmitter Interrupt Enable Register */
  124:  volatile CAN1TXDLRSTR _CAN1TXDLR;                          /* MSCAN 1 Transmit Data Length Register */
  125:  volatile CAN1TXDSR0STR _CAN1TXDSR0;                        /* MSCAN 1 Transmit Data Segment Register 0 */
  126:  volatile CAN1TXDSR1STR _CAN1TXDSR1;                        /* MSCAN 1 Transmit Data Segment Register 1 */
  127:  volatile CAN1TXDSR2STR _CAN1TXDSR2;                        /* MSCAN 1 Transmit Data Segment Register 2 */
  128:  volatile CAN1TXDSR3STR _CAN1TXDSR3;                        /* MSCAN 1 Transmit Data Segment Register 3 */
  129:  volatile CAN1TXDSR4STR _CAN1TXDSR4;                        /* MSCAN 1 Transmit Data Segment Register 4 */
  130:  volatile CAN1TXDSR5STR _CAN1TXDSR5;                        /* MSCAN 1 Transmit Data Segment Register 5 */
  131:  volatile CAN1TXDSR6STR _CAN1TXDSR6;                        /* MSCAN 1 Transmit Data Segment Register 6 */