s12sermon2r1.lst

Freescale HCS12 单片机系统监控

Metrowerks HC12-Assembler 
(c) COPYRIGHT METROWERKS 1987-2003

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    1    1                      ;.pagewidth  120t
    2    2                      ;*********************************************************************
    3    3                      ;* Title:  S12SerMonxrx.asm        Copyright (c) Motorola 2003
    4    4                      ;*********************************************************************
    5    5                      ;* Author: Jim Sibigtroth - Motorola TSPG - 8/16 Bit Division
    6    6                      ;* Author: Jim Williams - Motorola TSPG - 8/16 Bit Division
    7    7                      ;*
    8    8                      ;* Description: Bootloader/Monitor program for HCS9S12
    9    9                      ;* bootloader will reside in 2K of block protected memory at the
   10   10                      ;* end of the memory map of an HCS9S12 MCU ($F7FF-$FFFF).
   11   11                      ;*
   12   12                      ;* Since this code is located in the vector space, all interrupt
   13   13                      ;* vectors will be mirrored to the pseudo vector table in user
   14   14                      ;* erasable and reprogrammable flash memory just before the start
   15   15                      ;* of the protected bootloader code.
   16   16                      ;*
   17   17                      ;* If a non-FFFF user reset vector is programmed into the
   18   18                      ;* pseudo-reset vector, the bootloader will jump to that routine
   19   19                      ;* so the user can control all options including write-once bits.
   20   20                      ;*
   21   21                      ;* This monitor program implements 23 primitive monitor commands that
   22   22                      ;* are very similar to BDM commands. Third-party tool vendors can
   23   23                      ;* adapt their existing BDM-based tools to work through a serial I/O
   24   24                      ;* cable rather than a BDM pod, simply by providing a set of alternate
   25   25                      ;* interface routines. Although this monitor approach has some
   26   26                      ;* limitations compared to the BDM approach, it provides a free or
   27   27                      ;* very low cost alternative for the most cost-sensitive users.
   28   28                      ;*
   29   29                      ;* This monitor uses SCI0 as the primary interface to the target MCU
   30   30                      ;* system and SCI0 Rx interrupts are used to break out of a running
   31   31                      ;* user program. This implies that some monitor functions will not be
   32   32                      ;* available if the I bit in the CCR is not clear during execution of
   33   33                      ;* the user's program. During debug of user initialization programs
   34   34                      ;* and interrupt service routines when the I bit is not clear, trace
   35   35                      ;* and breakpoint functions still work as expected because these
   36   36                      ;* functions use on-chip breakpoint logic. 
   37   37                      ;*
   38   38                      ;*
   39   39                      ;*
   40   40                      ;* Revision History: not yet released
   41   41                      ;* Rev #     Date      Who     Comments
   42   42                      ;* -----  -----------  ------  ---------------------------------------
   43   43                      ;*  2.00   04-SEP-03   JPW     First Release.
   44   44                      ;*  2.01   03-DEC-03   JPW     MC9S12NE64 support added, fixed user jump table,
   45   45                      ;*                             fixed PLL/Timer Ch.7 corruption 
   46   46                      ;*                             Added Flash/EEPROM support > 12.8MHz OSC
   47   47                      ;
   48   48                      ;
   49   49          0000 0116   softwareID1:  equ   $0116     ;Software revision (date)
   50   50          0000 2004   softwareID2:  equ   $2004     ;Software revision (year)
   51   51          0000 0201   softwareID3:  equ   $0201     ;Software revision (ver)
   52   52                      
   53   53                      ;*
   54   54                      ;*
   55   55                      ;*********************************************************************
   56   56                      ;*********************************************************************
   57   57                      ;* Motorola reserves the right to make changes without further notice
   58   58                      ;* to any product herein to improve reliability, function, or design.
   59   59                      ;* Motorola does not assume any liability arising out of the
   60   60                      ;* application or use of any product, circuit, or software described
   61   61                      ;* herein; neither does it convey any license under its patent rights
   62   62                      ;* nor the rights of others.  Motorola products are not designed,
   63   63                      ;* intended, or authorized for use as components in systems intended
   64   64                      ;* for surgical implant into the body, or other applications intended

Metrowerks HC12-Assembler 
(c) COPYRIGHT METROWERKS 1987-2003

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   65   65                      ;* to support life, or for any other application in which the failure
   66   66                      ;* of the Motorola product could create a situation where personal
   67   67                      ;* injury or death may occur.  Should Buyer purchase or use Motorola
   68   68                      ;* products for any such intended or unauthorized application, Buyer
   69   69                      ;* shall indemnify and hold Motorola and its officers, employees,
   70   70                      ;* subsidiaries, affiliates, and distributors harmless against all
   71   71                      ;* claims, costs, damages, and expenses, and reasonable attorney fees
   72   72                      ;* arising out of, directly or indirectly, any claim of personal
   73   73                      ;* injury or death associated with such unintended or unauthorized
   74   74                      ;* use, even if such claim alleges that Motorola was negligent
   75   75                      ;* regarding the design or manufacture of the part.
   76   76                      ;*
   77   77                      ;* Motorola is a registered trademark of Motorola, Inc.
   78   78                      ;*********************************************************************
   79   79                      
   80   80                                  XDEF Startup         ;make symbol visible to the MW linker
   81   81                      ;*********************************************************************
   82   82                      ;* Include standard definitions that are common to all derivatives
   83   83                      ;*********************************************************************
   84   84                      ;             base    10           ;ensure default number base to decimal
  602   89                      ;*********************************************************************
  603   90                      ;* general equates for bootloader/monitor program valid for all
  604   91                      ;* derivatives
  605   92                      ;*********************************************************************
  606   93          0000 F800   BootStart:   equ    $F800         ;start of protected boot block
  607   94          0000 3FFF   RamLast:     equ    $3fff         ;last RAM location (all devices)
  608   95          0000 8000   Window:      equ    $8000         ;PPAGE Window start
  609   96          0000 4000   RomStart:    equ    $4000         ;start of flash
  610   97          0000 0080   VecTabSize:  equ    $80           ;size of vector table
  611   98          0000 FF80   VectorTable: equ    $10000-VecTabSize ;start of vector table
  612   99          0000 F780   PVecTable:   equ    BootStart-VecTabSize ;start of pseudo vector table
  613  100          0000 FF00   FProtStart:  equ    $FF00         ;start of FLASH protection/security
  614  101          0000 00C7   FProtBlksz:  equ    $C7           ;protect code for boot block ($C7 2K)
  615  102                      ;FProtBlksz:  equ    $FF           ;protect code for boot block (none)
  616  103          0000 00BE   FSecure:     equ    $BE           ;Disable Security and backdoor access
  617  104                      ;FSecure:     equ    $00           ;Enable Security and backdoor access
  618  105                      
  619  106          0000 5DC0   BusFreq:     equ    ((OscFreq/(initREFDV+1))*(initSYNR+1))
  620  107          0000 000D   baud115200:  equ    (BusFreq/16)*10/1152  ;sets baud rate to 115,200
  621  108          0000 05DC   longBreak:   equ    1500          ;delay time for >30-bit break
  622  109                      ; make TxD low at least 300us (30 bits @ 115200 baud)
  623  110                      ; 5~ * 42ns/~ * 1500 = 315us (not exact, just >30 bit times)
  624  111          0000 000D   asciiCR:     equ    $0D           ;ascii carriage return
  625  112                      
  626  113          0000 00CA   flagReg:     equ    SCI0CR1       ;SCI control1 reg of SCI0
  627  114          0000 0008   RunFlag:     equ    WAKE          ;SCI Wake bit used as run/mon flag
  628  115          0000 0020   ArmFlag:     equ    RSRC          ;SCI RSRC bit used for ARM storage
  629  116          0000 0004   TraceFlag:   equ    ILT           ;SCI Idle bit used as trace flag
  630  117                      ; 1=SWI caused by return from Trace1; 0=SWI from breakpoint or DBG
  631  118                      
  632  119          0000 000C   initSCI0CR2: equ    $0C           ;SCI0 Control Register 2
  633  120          0000 0080   traceOne:    equ    $80           ;BKPCT0 pattern for trace1 cmd
  634  121                      ;
  635  122                      ;CPU HCS12 CCR immediately after reset is:
  636  123          0000 00D0   initUCcr:    equ    %11010000     ;initial value for user's CCR
  637  124                      ;                    SX-I----     ;I interrupts masked
  638  125                      								  ;(SXHINZVC=11x1xxxx).
  639  126                      
  640  127          0000 00E0   ErrNone:     equ    $E0           ;code for no errors
  641  128          0000 00E1   ErrCmnd:     equ    $E1           ;command not recognized
  642  129          0000 00E2   ErrRun:      equ    $E2           ;command not allowed in run mode
  643  130          0000 00E3   ErrSP:       equ    $E3           ;SP was out of range
  644  131          0000 00E4   ErrWriteSP:  equ    $E4           ;attempted to write bad SP value
  645  132          0000 00E5   ErrByteNVM:  equ    $E5           ;write_byte attempt NVM

Metrowerks HC12-Assembler 
(c) COPYRIGHT METROWERKS 1987-2003

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  646  133          0000 00E6   ErrFlash:    equ    $E6           ;FACCERR or FPVIOL error
  647  134          0000 00E7   ErrFlErase:  equ    $E7           ;Error code not implemented
  648  135          0000 00E8   ErrGoVec:    equ    $E8           ;Error code not implemented
  649  136          0000 00E9   ErrEeErase   equ    $E9			  ;EACCERR or EPVIOL error
  650  137                      
  651  138          0000 0002   StatHalt:    equ    $02           ;stopped by Halt command
  652  139          0000 0004   StatTrace:   equ    $04           ;returned from a Trace1 command
  653  140          0000 0006   StatBreak:   equ    $06           ;Breakpoint or DBG (SWI) request
  654  141          0000 0008   StatCold:    equ    $08           ;just did a cold reset
  655  142          0000 000C   StatWarm:    equ    $0C           ;warm start because int with bad SP
  656  143                      
  657  144                      ;*********************************************************************
  658  145                      ;* User CPU registers stack frame...
  659  146                      ;*   +0  UCcr   <- Monitor's SP
  660  147                      ;*   +1  UDreg   (B:A)
  661  148                      ;*   +3  UXreg
  662  149                      ;*   +5  UYreg
  663  150                      ;*   +7  UPc
  664  151                      ;*   +9  ---     <- User's SP
  665  152                      ; Offsets from actual SP to user CPU regs while in monitor
  666  153                      ;*********************************************************************
  667  154                      
  668  155          0000 0000   UCcr:        equ    0             ;user's CCR register
  669  156          0000 0001   UDreg:       equ    1             ;user's D register (B:A)
  670  157          0000 0003   UXreg:       equ    3             ;user's X register
  671  158          0000 0005   UYreg:       equ    5             ;user's Y register