s12sermon2r1.dbg

Freescale HCS12 单片机系统监控

;.pagewidth  120t
;*********************************************************************
;* Title:  S12SerMonxrx.asm        Copyright (c) Motorola 2003
;*********************************************************************
;* Author: Jim Sibigtroth - Motorola TSPG - 8/16 Bit Division
;* Author: Jim Williams - Motorola TSPG - 8/16 Bit Division
;*
;* Description: Bootloader/Monitor program for HCS9S12
;* bootloader will reside in 2K of block protected memory at the
;* end of the memory map of an HCS9S12 MCU ($F7FF-$FFFF).
;*
;* Since this code is located in the vector space, all interrupt
;* vectors will be mirrored to the pseudo vector table in user
;* erasable and reprogrammable flash memory just before the start
;* of the protected bootloader code.
;*
;* If a non-FFFF user reset vector is programmed into the
;* pseudo-reset vector, the bootloader will jump to that routine
;* so the user can control all options including write-once bits.
;*
;* This monitor program implements 23 primitive monitor commands that
;* are very similar to BDM commands. Third-party tool vendors can
;* adapt their existing BDM-based tools to work through a serial I/O
;* cable rather than a BDM pod, simply by providing a set of alternate
;* interface routines. Although this monitor approach has some
;* limitations compared to the BDM approach, it provides a free or
;* very low cost alternative for the most cost-sensitive users.
;*
;* This monitor uses SCI0 as the primary interface to the target MCU
;* system and SCI0 Rx interrupts are used to break out of a running
;* user program. This implies that some monitor functions will not be
;* available if the I bit in the CCR is not clear during execution of
;* the user's program. During debug of user initialization programs
;* and interrupt service routines when the I bit is not clear, trace
;* and breakpoint functions still work as expected because these
;* functions use on-chip breakpoint logic. 
;*
;*
;*
;* Revision History: not yet released
;* Rev #     Date      Who     Comments
;* -----  -----------  ------  ---------------------------------------
;*  2.00   04-SEP-03   JPW     First Release.
;*  2.01   03-DEC-03   JPW     MC9S12NE64 support added, fixed user jump table,
;*                             fixed PLL/Timer Ch.7 corruption 
;*                             Added Flash/EEPROM support > 12.8MHz OSC
;
;
softwareID1:  equ   $0116     ;Software revision (date)
softwareID2:  equ   $2004     ;Software revision (year)
softwareID3:  equ   $0201     ;Software revision (ver)

;*
;*
;*********************************************************************
;*********************************************************************
;* Motorola reserves the right to make changes without further notice
;* to any product herein to improve reliability, function, or design.
;* Motorola does not assume any liability arising out of the
;* application or use of any product, circuit, or software described
;* herein; neither does it convey any license under its patent rights
;* nor the rights of others.  Motorola products are not designed,
;* intended, or authorized for use as components in systems intended
;* for surgical implant into the body, or other applications intended
;* to support life, or for any other application in which the failure
;* of the Motorola product could create a situation where personal
;* injury or death may occur.  Should Buyer purchase or use Motorola
;* products for any such intended or unauthorized application, Buyer
;* shall indemnify and hold Motorola and its officers, employees,
;* subsidiaries, affiliates, and distributors harmless against all
;* claims, costs, damages, and expenses, and reasonable attorney fees
;* arising out of, directly or indirectly, any claim of personal
;* injury or death associated with such unintended or unauthorized
;* use, even if such claim alleges that Motorola was negligent
;* regarding the design or manufacture of the part.
;*
;* Motorola is a registered trademark of Motorola, Inc.
;*********************************************************************

            XDEF Startup         ;make symbol visible to the MW linker
;*********************************************************************
;* Include standard definitions that are common to all derivatives
;*********************************************************************
;             base    10           ;ensure default number base to decimal
;*********************************************************************
;* general equates for bootloader/monitor program valid for all
;* derivatives
;*********************************************************************
BootStart:   equ    $F800         ;start of protected boot block
RamLast:     equ    $3fff         ;last RAM location (all devices)
Window:      equ    $8000         ;PPAGE Window start
RomStart:    equ    $4000         ;start of flash
VecTabSize:  equ    $80           ;size of vector table
VectorTable: equ    $10000-VecTabSize ;start of vector table
PVecTable:   equ    BootStart-VecTabSize ;start of pseudo vector table
FProtStart:  equ    $FF00         ;start of FLASH protection/security
FProtBlksz:  equ    $C7           ;protect code for boot block ($C7 2K)
;FProtBlksz:  equ    $FF           ;protect code for boot block (none)
FSecure:     equ    $BE           ;Disable Security and backdoor access
;FSecure:     equ    $00           ;Enable Security and backdoor access

BusFreq:     equ    ((OscFreq/(initREFDV+1))*(initSYNR+1))
baud115200:  equ    (BusFreq/16)*10/1152  ;sets baud rate to 115,200
longBreak:   equ    1500          ;delay time for >30-bit break
; make TxD low at least 300us (30 bits @ 115200 baud)
; 5~ * 42ns/~ * 1500 = 315us (not exact, just >30 bit times)
asciiCR:     equ    $0D           ;ascii carriage return

flagReg:     equ    SCI0CR1       ;SCI control1 reg of SCI0
RunFlag:     equ    WAKE          ;SCI Wake bit used as run/mon flag
ArmFlag:     equ    RSRC          ;SCI RSRC bit used for ARM storage
TraceFlag:   equ    ILT           ;SCI Idle bit used as trace flag
; 1=SWI caused by return from Trace1; 0=SWI from breakpoint or DBG

initSCI0CR2: equ    $0C           ;SCI0 Control Register 2
traceOne:    equ    $80           ;BKPCT0 pattern for trace1 cmd
;
;CPU HCS12 CCR immediately after reset is:
initUCcr:    equ    %11010000     ;initial value for user's CCR
;                    SX-I----     ;I interrupts masked
								  ;(SXHINZVC=11x1xxxx).

ErrNone:     equ    $E0           ;code for no errors
ErrCmnd:     equ    $E1           ;command not recognized
ErrRun:      equ    $E2           ;command not allowed in run mode
ErrSP:       equ    $E3           ;SP was out of range
ErrWriteSP:  equ    $E4           ;attempted to write bad SP value
ErrByteNVM:  equ    $E5           ;write_byte attempt NVM
ErrFlash:    equ    $E6           ;FACCERR or FPVIOL error
ErrFlErase:  equ    $E7           ;Error code not implemented
ErrGoVec:    equ    $E8           ;Error code not implemented
ErrEeErase   equ    $E9			  ;EACCERR or EPVIOL error

StatHalt:    equ    $02           ;stopped by Halt command
StatTrace:   equ    $04           ;returned from a Trace1 command
StatBreak:   equ    $06           ;Breakpoint or DBG (SWI) request
StatCold:    equ    $08           ;just did a cold reset
StatWarm:    equ    $0C           ;warm start because int with bad SP

;*********************************************************************
;* User CPU registers stack frame...
;*   +0  UCcr   <- Monitor's SP
;*   +1  UDreg   (B:A)
;*   +3  UXreg
;*   +5  UYreg
;*   +7  UPc
;*   +9  ---     <- User's SP
; Offsets from actual SP to user CPU regs while in monitor
;*********************************************************************

UCcr:        equ    0             ;user's CCR register
UDreg:       equ    1             ;user's D register (B:A)
UXreg:       equ    3             ;user's X register
UYreg:       equ    5             ;user's Y register
UPc:         equ    7             ;user's PC
SPOffset:    equ    9             ;offset of stack pointer while in monitor

MaxMonStack  equ   35             ;maximum number of bytes used by Monitor
LowSPLimit   equ   RamStart+MaxMonStack-SPOffset
HighSPLimit  equ   RamLast-SPOffset+1

; named locations on stack if SWI with bad SP value
;*********************************************************************
;* Start of code and/or constant data
;*********************************************************************
             org    BootStart      ;beginning of protected flash
;*********************************************************************
;* Main startup program - real reset vector points to here
;*********************************************************************
;*********************************************************************
;  THIS LOCKS RAM / REGS / AND EEPROM BY USING ONLY WRITE USER CODE 
;  WILL NOT EFFECT THESE SETTINGS...This is for derivative compatibility
;  Please refer to EB388
;*********************************************************************
ColdStart:  
Startup:
main:
             movb  #$00,INITRG    ;set registers at $0000 
             movb  #$39,INITRM    ;set ram to end at $3fff 
             brclr  MEMSIZ0,eep_sw1+eep_sw0,ColdStart1  ;Check if device has EEprom
             movb  #$09,INITEE    ;set eeprom to end at $0fff 
             
ColdStart1:     clra                 ;A=0=cold start; see tsta @ ChkCold

;**********************************************************************
; Decide whether to go to user reset or bootloader/monitor
;**********************************************************************
;  (a) default to monitor if high byte user pseudo-vector is erased ($FF)
;**********************************************************************
             ldab   vector00-($10000-BootStart) ;check for user reset Vector
             comb                 ;if erased COMB result will be 0
             beq    Monitor       ;default to monitor if no vector

;**********************************************************************
; Test the state of some  pins to force entering the monitor
;   Depending on the hardware configuration enable/disable/modify the
;   sections below
;**********************************************************************
             bset   SwPullup,mSwPullup ;enable pullup on force monitor sw
             bset   PPSS,PPSS0    ;enable pullup on RxD0 pin
             bset   PERS,PERS0    ;on RxD0 pin
             clrb
             dbne   b,*           ;delay to allow sw pin to pull up
;**********************************************************************
;  (b) force monitor if SwPort bit SWITCH = 0 
;  Note: this port is configured after reset as input with pull-up
;  With no connection to this pin the monitor jumps to run mode
;**********************************************************************
             ldab   SwPort        ;get port value
             bitb   #Switch       ;test the sw bit
             beq    Monitor

;**********************************************************************
;  (c) force monitor if RxD low (from host)  PORTS bit 0
;      This is true if the host holds RxD on break level
;  Note: this port is configured after reset as input with pull-up
;**********************************************************************
             brclr  PTS,PTS0,Monitor ;to monitor if RxD low
             bclr   PPSS,PPSS0    ;restore reset state on RxD0 pin
             bclr   PERS,PERS0    ;restore reset state on RxD1 pin

;**********************************************************************
;  finally jump to the user application (by pseudo vector)
;**********************************************************************
             jmp    [vector00-($10000-BootStart),pcr] ;go where
                                        ;user reset vector points
;*********************************************************************
;  Formal start of Monitor code
;*********************************************************************
Monitor:
; Initialize clock generator and PLL
;
             bclr    SwPullup,mSwPullup ;restore reset state
             bclr    CLKSEL,PLLSEL      ;disengage PLL to system
             bset    PLLCTL,PLLON       ;turn on PLL
             movb    #initSYNR,SYNR     ;set PLL multiplier 
             movb    #initREFDV,REFDV   ;set PLL divider
             nop
             nop
             brclr   CRGFLG,LOCK,*+0    ;while (!(crg.crgflg.bit.lock==1))
             bset    CLKSEL,PLLSEL      ;engage PLL to system
;
; set flash/EEPROM clock to 200 kHz
;
  IF OscFreq >= 12800
  ELSE	
             movb  #((OscFreq/200)-1),FCLKDIV ;Flash CLK = 200 kHz
             movb  #((OscFreq/200)-1),ECLKDIV    ;Eeprom CLK = 200 kHz
  ENDIF
;
; Set stack pointer to last (highest) RAM location
;
stackInit:   lds    #RamLast+1    ;point one past RAM

; Setup initial user CPU register values (user register stack frame)
;   A holds the initial state value
initUregs:   ldx   BootStart-2    ;load user reset vector
             pshx                 ;$00 to user UPc      $3FFe
             ldx   #$0000
             pshx                 ;$00 to user UYreg    $3ffc
             pshx                 ;$00 to user UXreg    $3ffa
             pshx                 ;$00 to user UDreg    $3ff8
             ldab  #initUCcr      ;initial value for user CCR
             pshb                 ;to UCcr              $3ff7