__projnav.log

使用xilinx公司的FPGA实现了七段码的定时器时钟程序

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd h:\exercise_ise\7seg_led/_ngo -uc
segled.ucf -p xc3s200-pq208-4 segled.ngc segled.ngd 

Reading NGO file 'H:/exercise_ise/7seg_led/segled.ngc' ...

Applying constraints in "segled.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "segled.ngd" ...

Writing NGDBUILD log file "segled.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200pq208-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          54 out of   3,840    1%
  Number of 4 input LUTs:              70 out of   3,840    1%
Logic Distribution:
  Number of occupied Slices:                           57 out of   1,920    2%
    Number of Slices containing only related logic:      57 out of      57  100%
    Number of Slices containing unrelated logic:          0 out of      57    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            108 out of   3,840    2%
  Number used as logic:                 70
  Number used as a route-thru:          38
  Number of bonded IOBs:               13 out of     141    9%
    IOB Flip Flops:                    12
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  1,221
Additional JTAG gate count for IOBs:  624
Peak Memory Usage:  107 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "segled_map.mrp" for details.




Started process "Place & Route".




Constraints file: segled.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
D:/Xilinx ISE 7.1i.
   "segled" is an NCD, version 3.1, device xc3s200, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            13 out of 141     9%
      Number of LOCed IOBs            13 out of 13    100%

   Number of Slices                   57 out of 1920    2%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98979f) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.8
.....
Phase 4.8 (Checksum:99046b) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file segled.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 385 unrouted;       REAL time: 2 secs 

Phase 2: 352 unrouted;       REAL time: 2 secs 

Phase 3: 128 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 


WARNING:CLK Net:divclk
may have excessive skew because 8 CLK pins and 1 NON_CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX1| No   |   32 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+
|              divclk |         Local|      |    9 |  1.031     |  2.857      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  74 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file segled.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
D:/Xilinx ISE 7.1i.
   "segled" is an NCD, version 3.1, device xc3s200, package pq208, speed -4

Analysis completed Wed Mar 22 15:40:07 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 3 secs 


Project Navigator Auto-Make Log File
-------------------------------------







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "segled.v"
Module <segled> compiled
No errors in compilation
Analysis of file <"segled.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <segled>.
WARNING:Xst:905 - "segled.v" line 83: The signals <secseg1, secseg2, minseg1, minseg2> are missing in the sensitivity list of always block.
Module <segled> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <segled>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <segled>.
    Related source file is "segled.v".
WARNING:Xst:1780 - Signal <scanclk> is never used or assigned.
    Found 16x8-bit ROM for signal <secseg1>.
    Found 16x8-bit ROM for signal <minseg1>.
    Found 1-of-4 decoder for signal <a>.
    Found 8-bit 4-to-1 multiplexer for signal <seg>.
    Found 28-bit comparator greatequal for signal <$n0000> created at line 45.
    Found 4-bit comparator greatequal for signal <$n0002> created at line 56.
    Found 4-bit comparator greatequal for signal <$n0024> created at line 59.
    Found 4-bit comparator lessequal for signal <$n0025> created at line 62.
    Found 4-bit comparator less for signal <$n0026> created at line 59.
    Found 4-bit comparator less for signal <$n0027> created at line 56.
    Found 4-bit comparator lessequal for signal <$n0028> created at line 65.
    Found 4-bit comparator greater for signal <$n0029> created at line 62.
    Found 1-bit register for signal <divclk>.
    Found 28-bit up counter for signal <divcounter>.
    Found 4-bit up counter for signal <mincounter1>.
    Found 4-bit up counter for signal <mincounter2>.
    Found 9-bit up counter for signal <scan>.
    Found 4-bit up counter for signal <seccounter1>.
    Found 4-bit up counter for signal <seccounter2>.
    Summary:
	inferred   2 ROM(s).
	inferred   6 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   8 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <segled> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
 16x8-bit ROM                      : 2
# Counters                         : 6
 28-bit up counter                 : 1
 4-bit up counter                  : 4
 9-bit up counter                  : 1
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 8
 28-bit comparator greatequal      : 1
 4-bit comparator greatequal       : 2
 4-bit comparator greater          : 1
 4-bit comparator less             : 2
 4-bit comparator lessequal        : 2
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0002>, <Mcompar__n0027> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_6> are dual, second instance is removed
WARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0024>, <Mcompar__n0026> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_5> are dual, second instance is removed
WARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0025>, <Mcompar__n0029> of unit <LPM_COMPARE_4> and unit <LPM_COMPARE_8> are dual, second instance is removed

Optimizing unit <segled> ...
Loading device for application Rf_Device from file '3s200.nph' in environment D:/Xilinx ISE 7.1i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block segled, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-4 

 Number of Slices:                      63  out of   1920     3%  
 Number of Slice Flip Flops:            54  out of   3840     1%  
 Number of 4 input LUTs:               105  out of   3840     2%  
 Number of bonded IOBs:                 13  out of    141     9%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 38    |
divclk:Q                           | NONE                   | 16    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.935ns (Maximum Frequency: 126.024MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.106ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd h:\exercise_ise\7seg_led/_ngo -uc
segled.ucf -p xc3s200-pq208-4 segled.ngc segled.ngd 

Reading NGO file 'H:/exercise_ise/7seg_led/segled.ngc' ...

Applying constraints in "segled.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "segled.ngd" ...

Writing NGDBUILD log file "segled.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200pq208-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          54 out of   3,840    1%
  Number of 4 input LUTs:              73 out of   3,840    1%
Logic Distribution:
  Number of occupied Slices:                           58 out of   1,920    3%
    Number of Slices containing only related logic:      58 out of      58  100%
    Number of Slices containing unrelated logic:          0 out of      58    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            111 out of   3,840    2%
  Number used as logic:                 73
  Number used as a route-thru:          38
  Number of bonded IOBs:               13 out of     141    9%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  1,143
Additional JTAG gate count for IOBs:  624
Peak Memory Usage:  107 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.