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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"ERROR:HDLCompilers:26 - "segled.v" line 45 unexpected token: '8'ERROR:HDLCompilers:26 - "segled.v" line 47 unexpected token: '8'ERROR:HDLCompilers:26 - "segled.v" line 64 unexpected token: '4'ERROR:HDLCompilers:28 - "segled.v" line 69 'mincounter' has not been declaredERROR:HDLCompilers:28 - "segled.v" line 73 'seccounter' has not been declaredERROR:HDLCompilers:28 - "segled.v" line 75 'seccounter' has not been declaredERROR:HDLCompilers:26 - "segled.v" line 82 expecting '(', found 'scanclk'ERROR:HDLCompilers:26 - "segled.v" line 83 expecting 'end', found '2'Module <segled> compiledERROR:HDLCompilers:26 - "segled.v" line 83 expecting 'endmodule', found ''b'Analysis of file <"segled.prj"> failed.--> Total memory usage is 77020 kilobytesNumber of errors : 9 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"ERROR:HDLCompilers:26 - "segled.v" line 45 unexpected token: '28'ERROR:HDLCompilers:26 - "segled.v" line 64 unexpected token: '4'ERROR:HDLCompilers:28 - "segled.v" line 69 'mincounter' has not been declaredERROR:HDLCompilers:28 - "segled.v" line 73 'seccounter' has not been declaredERROR:HDLCompilers:28 - "segled.v" line 75 'seccounter' has not been declaredERROR:HDLCompilers:26 - "segled.v" line 82 expecting '(', found 'scanclk'ERROR:HDLCompilers:26 - "segled.v" line 83 expecting 'end', found '2'Module <segled> compiledERROR:HDLCompilers:26 - "segled.v" line 83 expecting 'endmodule', found ''b'Analysis of file <"segled.prj"> failed.--> Total memory usage is 77020 kilobytesNumber of errors : 8 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"ERROR:HDLCompilers:26 - "segled.v" line 64 unexpected token: '4'ERROR:HDLCompilers:28 - "segled.v" line 69 'mincounter' has not been declaredERROR:HDLCompilers:28 - "segled.v" line 73 'seccounter' has not been declaredERROR:HDLCompilers:28 - "segled.v" line 75 'seccounter' has not been declaredERROR:HDLCompilers:26 - "segled.v" line 82 expecting '(', found 'scanclk'ERROR:HDLCompilers:26 - "segled.v" line 83 expecting 'end', found '2'Module <segled> compiledERROR:HDLCompilers:26 - "segled.v" line 83 expecting 'endmodule', found ''b'Analysis of file <"segled.prj"> failed.--> Total memory usage is 77020 kilobytesNumber of errors : 7 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"ERROR:HDLCompilers:26 - "segled.v" line 82 expecting '(', found 'scanclk'ERROR:HDLCompilers:26 - "segled.v" line 83 expecting 'end', found '2'Module <segled> compiledERROR:HDLCompilers:26 - "segled.v" line 83 expecting 'endmodule', found ''b'Analysis of file <"segled.prj"> failed.--> Total memory usage is 77020 kilobytesNumber of errors : 3 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"ERROR:HDLCompilers:26 - "segled.v" line 104 expecting '(', found 'seccounter1'ERROR:HDLCompilers:26 - "segled.v" line 105 expecting 'end', found '4'Module <segled> compiledERROR:HDLCompilers:26 - "segled.v" line 105 expecting 'endmodule', found ''b'Analysis of file <"segled.prj"> failed.--> Total memory usage is 77020 kilobytesNumber of errors : 3 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"Module <segled> compiledERROR:HDLCompilers:247 - "segled.v" line 48 Reference to scalar wire 'divclk' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "segled.v" line 48 Illegal left hand side of blocking assignmentWARNING:HDLCompilers:192 - "segled.v" line 81 Most significant bit operand in part-select of vector reg 'scan' is out of rangeAnalysis of file <"segled.prj"> failed.--> Total memory usage is 77020 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 1 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"Module <segled> compiledERROR:HDLCompilers:247 - "segled.v" line 48 Reference to scalar wire 'divclk' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "segled.v" line 48 Illegal left hand side of nonblocking assignmentWARNING:HDLCompilers:192 - "segled.v" line 81 Most significant bit operand in part-select of vector reg 'scan' is out of rangeAnalysis of file <"segled.prj"> failed.--> Total memory usage is 77020 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 1 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"Module <segled> compiledWARNING:HDLCompilers:192 - "segled.v" line 81 Most significant bit operand in part-select of vector reg 'scan' is out of rangeNo errors in compilationAnalysis of file <"segled.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================WARNING:HDLCompilers:192 - "segled.v" line 81 Most significant bit operand in part-select of vector reg 'scan' is out of rangeAnalyzing top module <segled>.ERROR:Xst:792 - "segled.v" line 81: Index 8 is not in range of signal <scan>. Found 1 error(s). Aborting synthesis.--> Total memory usage is 77020 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 2 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "segled.v"Module <segled> compiledNo errors in compilationAnalysis of file <"segled.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <segled>.Module <segled> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <segled>. Related source file is "segled.v".WARNING:Xst:1780 - Signal <scanclk> is never used or assigned. Found 16x8-bit ROM for signal <secseg1>. Found 16x8-bit ROM for signal <minseg1>. Found 4-bit register for signal <a>. Found 8-bit register for signal <seg>. Found 28-bit comparator greatequal for signal <$n0000> created at line 45. Found 4-bit comparator greatequal for signal <$n0002> created at line 56. Found 8-bit 4-to-1 multiplexer for signal <$n0008> created at line 81. Found 1-of-4 decoder for signal <$n0009> created at line 81. Found 4-bit comparator greatequal for signal <$n0026> created at line 59. Found 4-bit comparator lessequal for signal <$n0027> created at line 62. Found 4-bit comparator less for signal <$n0028> created at line 59. Found 4-bit comparator less for signal <$n0029> created at line 56. Found 4-bit comparator lessequal for signal <$n0030> created at line 65. Found 4-bit comparator greater for signal <$n0031> created at line 62. Found 1-bit register for signal <divclk>. Found 28-bit up counter for signal <divcounter>. Found 4-bit up counter for signal <mincounter1>. Found 4-bit up counter for signal <mincounter2>. Found 9-bit up counter for signal <scan>. Found 4-bit up counter for signal <seccounter1>. Found 4-bit up counter for signal <seccounter2>. Summary: inferred 2 ROM(s). inferred 6 Counter(s). inferred 13 D-type flip-flop(s). inferred 8 Comparator(s). inferred 8 Multiplexer(s). inferred 1 Decoder(s).Unit <segled> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 2 16x8-bit ROM : 2# Counters : 6 28-bit up counter : 1 4-bit up counter : 4 9-bit up counter : 1# Registers : 3 1-bit register : 1 4-bit register : 1 8-bit register : 1# Comparators : 8 28-bit comparator greatequal : 1 4-bit comparator greatequal : 2 4-bit comparator greater : 1 4-bit comparator less : 2 4-bit comparator lessequal : 2# Multiplexers : 1 8-bit 4-to-1 multiplexer : 1# Decoders : 1 1-of-4 decoder : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0002>, <Mcompar__n0029> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_6> are dual, second instance is removedWARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0026>, <Mcompar__n0028> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_5> are dual, second instance is removedWARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0027>, <Mcompar__n0031> of unit <LPM_COMPARE_4> and unit <LPM_COMPARE_8> are dual, second instance is removedOptimizing unit <segled> ...WARNING:Xst:1426 - The value init of the FF/Latch seg_0 hinder the constant cleaning in the block segled. You should achieve better results by setting this init to 1.Loading device for application Rf_Device from file '3s200.nph' in environment D:/Xilinx ISE 7.1i.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block segled, actual ratio is 3.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200pq208-4 Number of Slices: 62 out of 1920 3% Number of Slice Flip Flops: 66 out of 3840 1% Number of 4 input LUTs: 102 out of 3840 2% Number of bonded IOBs: 13 out of 141 9% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 50 |divclk:Q | NONE | 16 |-----------------------------------+------------------------+-------+INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary:---------------Speed Grade: -4 Minimum period: 7.935ns (Maximum Frequency: 126.024MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 7.165ns Maximum combinational path delay: No path found=========================================================================
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