segled.par

使用xilinx公司的FPGA实现了七段码的定时器时钟程序

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

NUDT-27BE4ECA55::  Wed Mar 22 15:54:09 2006

par -w -intstyle ise -ol std -t 1 segled_map.ncd segled.ncd segled.pcf 


Constraints file: segled.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
D:/Xilinx ISE 7.1i.
   "segled" is an NCD, version 3.1, device xc3s200, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            13 out of 141     9%
      Number of LOCed IOBs            13 out of 13    100%

   Number of Slices                   61 out of 1920    3%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9897b7) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.8
....
Phase 4.8 (Checksum:991203) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file segled.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 389 unrouted;       REAL time: 2 secs 

Phase 2: 368 unrouted;       REAL time: 2 secs 

Phase 3: 127 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 


WARNING:CLK Net:divclk
may have excessive skew because 9 CLK pins and 1 NON_CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX1| No   |   20 |  0.001     |  1.011      |
+---------------------+--------------+------+------+------------+-------------+
|              divclk |         Local|      |   10 |  1.487     |  2.766      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  74 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file segled.ncd



PAR done!