segled.twr

使用xilinx公司的FPGA实现了七段码的定时器时钟程序

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx ISE 7.1i/bin/nt/trce.exe -ise h:\exercise_ise\7seg_led\7seg_led.ise
-intstyle ise -e 3 -l 3 -s 4 -xml segled segled.ncd -o segled.twr segled.pcf


Design file:              segled.ncd
Physical constraint file: segled.pcf
Device,speed:             xc3s200,-4 (PRODUCTION 1.35 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
a<0>        |   11.059(R)|clk_BUFGP         |   0.000|
a<1>        |   11.061(R)|clk_BUFGP         |   0.000|
a<2>        |   10.771(R)|clk_BUFGP         |   0.000|
a<3>        |   10.812(R)|clk_BUFGP         |   0.000|
seg<0>      |   11.992(R)|clk_BUFGP         |   0.000|
seg<1>      |   11.535(R)|clk_BUFGP         |   0.000|
seg<2>      |   11.432(R)|clk_BUFGP         |   0.000|
seg<3>      |   11.034(R)|clk_BUFGP         |   0.000|
seg<4>      |   11.588(R)|clk_BUFGP         |   0.000|
seg<5>      |   11.774(R)|clk_BUFGP         |   0.000|
seg<6>      |   12.321(R)|clk_BUFGP         |   0.000|
seg<7>      |   11.624(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.186|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Mar 22 15:54:15 2006
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Peak Memory Usage: 83 MB