segled.v

使用xilinx公司的FPGA实现了七段码的定时器时钟程序

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:35:43 03/22/06
// Design Name:    
// Module Name:    segled
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module segled(seg,a,clk);
input clk;
output [7:0] seg;
output [3:0] a;
reg    [7:0] seg;
reg    [3:0] a;


reg    [27:0]  divcounter;
reg            divclk;
reg    [3:0]  seccounter1;
reg    [3:0]  seccounter2;
reg    [3:0]  mincounter1;
reg    [3:0]  mincounter2;
reg    [8:0]  scan;
reg    [1:0]  scanclk;
reg    [7:0]  secseg1;
reg    [7:0]  secseg2;
reg    [7:0]  minseg1;
reg    [7:0]  minseg2;

//divclk
always@(posedge clk)
     begin
	        if(divcounter>=28'b0001011111010111100000111111)   
			      begin
					     divcounter<=0;
						  divclk<=~divclk;
               end
			  else
					 divcounter<=divcounter+1;
      end
//count
always@(posedge divclk)
      begin
		     	if(seccounter1>=4'b1001) 
				   begin   
				        seccounter1<=4'b0000;
				        if(seccounter2>=4'b0101)
						     begin
							       seccounter2<=4'b0000;
									 if(mincounter1>=4'b1001)
									   begin
										     mincounter1<=4'b0000;
											  if(mincounter2>=4'b0101)
											    begin
												      mincounter2<=4'b0000;
												 end
											  else  mincounter2<=mincounter2+1;
										 end
									  else  mincounter1<=mincounter1+1;
								end
							else   seccounter2<=seccounter2+1;
					 end
				else   seccounter1<=seccounter1+1;
		end
//scan
always@(posedge clk)
      begin
		     scan<=scan+1;
      end
always@(scan)
      begin
           case (scan[8:7])
			       2'b00   :	begin
					                 	 seg<=secseg1;
											 a<=4'b0001;
                           end
                2'b01   :  begin
					                    seg<=secseg2;
											  a<=4'b0010;
                           end
                2'b10   :  begin   
					                    seg<=minseg1;
											  a<=4'b0100;
                           end
				    2'b11   :	begin
					                    seg<=minseg2;
											  a<=4'b1000;
                           end
            endcase
      end
//sigal second
always@(seccounter1)
      begin
		     case 	(seccounter1[3:0])   
			     4'b0000  :   secseg1<=8'b00000011;
				  4'b0001  :   secseg1<=8'b10011111;
				  4'b0010  :   secseg1<=8'b00100101;
				  4'b0011  :   secseg1<=8'b00001101;
				  4'b0100  :   secseg1<=8'b10011001;
				  4'b0101  :   secseg1<=8'b01001001;
				  4'b0110  :   secseg1<=8'b01000001;
				  4'b0111  :   secseg1<=8'b00011111;
				  4'b1000  :   secseg1<=8'b00000001;
				  4'b1001  :   secseg1<=8'b00001001;
				  default  :   secseg1<=8'b11111111;
			  endcase
       end
//singal decade
always@(seccounter2)
      begin
		     case 	(seccounter2[3:0])   
			     4'b0000  :   secseg2<=8'b00000011;
				  4'b0001  :   secseg2<=8'b10011111;
				  4'b0010  :   secseg2<=8'b00100101;
				  4'b0011  :   secseg2<=8'b00001101;
				  4'b0100  :   secseg2<=8'b10011001;
				  4'b0101  :   secseg2<=8'b01001001;
				  default  :   secseg2<=8'b11111111;
			  endcase
       end
//interrupt
always@(posedge divclk)
      begin
		     minseg1[0]<=~minseg1[0];
      end

//minites signal
always@(mincounter1)
      begin
		     case 	(mincounter1[3:0])   
			     4'b0000  :   minseg1[7:1]<=8'b0000001;
				  4'b0001  :   minseg1[7:1]<=8'b1001111;
				  4'b0010  :   minseg1[7:1]<=8'b0010010;
				  4'b0011  :   minseg1[7:1]<=8'b0000110;
				  4'b0100  :   minseg1[7:1]<=8'b1001100;
				  4'b0101  :   minseg1[7:1]<=8'b0100100;
				  4'b0110  :   minseg1[7:1]<=8'b0100000;
				  4'b0111  :   minseg1[7:1]<=8'b0001111;
				  4'b1000  :   minseg1[7:1]<=8'b0000000;
				  4'b1001  :   minseg1[7:1]<=8'b0000100;
				  default  :   minseg1[7:1]<=8'b1111111;
			  endcase
       end
//minites decade
always@(mincounter2)
      begin
		     case 	(mincounter2[3:0])   
			     4'b0000  :   minseg2<=8'b00000011;
				  4'b0001  :   minseg2<=8'b10011111;
				  4'b0010  :   minseg2<=8'b00100101;
				  4'b0011  :   minseg2<=8'b00001101;
				  4'b0100  :   minseg2<=8'b10011001;
				  4'b0101  :   minseg2<=8'b01001001;
				  default  :   minseg2<=8'b11111111;
			  endcase
       end

endmodule