📄 wireless.lst
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C51 COMPILER V8.02 WIRELESS 04/14/2006 12:17:22 PAGE 1
C51 COMPILER V8.02, COMPILATION OF MODULE WIRELESS
OBJECT MODULE PLACED IN wireless.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE wireless.c BROWSE DEBUG OBJECTEXTEND
line level source
1 /* wireless.c
2 ============================================================================================
3 ====
4 *
5 * This file is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTYT; without even the
6 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
7 *
8 * Author(s): Ole Saether
9 *
10 * NOTES:
11 *
12 * A frame is the time between each transmission of a packet.
13 * A frame is divided into NSLOTS time-slots. The duration of a time-slot is 1/fs, where fs is the ADC
14 * sampling frequency.
15 *
16 * The NOSYNC variable is used by the slave to keep track of how many frames have gone since it received a
17 * valid packet. It is incremented once each frame in the TIMER2 irq handler and cleared each time a packet
- is
18 * received. If the variable reaches the constant NSYNC (see below) the slave enters continuous receive mod
-e.
19 *
20 * The pin P0.2 is used to select slave (P0.2 = 1) or master (P0.2 = 0).
21 *
22 * $Date: 8.10.03 12:02 $
23 * $Revision: 1 $
24 *
25 *===========================================================================================
26 ==================
27 */
28 #include <reg24e1.h>
29 #define ADDR_INDEX 8 // Index to address bytes in RFConfig.buf
30 #define ADDR_COUNT 4 // Number of address bytes
31 #define FSZ 32 // Buffer size
32 #define FMASK FSZ-1
33 struct RFConfig
34 {
35 unsigned char n;
36 unsigned char buf[15];
37 };
38 typedef struct RFConfig RFConfig;
39 #define NSLOTS 24 // Number of samples in one packet
40 #define NSYNC 10 // #frames wo/packets before the slave enters receive mode
41 #define RXSLOT 14 // Wait from slot 14 to..
42 #define WTSLOT 21 // ..slot 21 for reception of a packet
43 #define SYNCSLOT 20 // When the slave receives a valid packet set the slot counter to this number
44 volatile unsigned char idata RxBuf[FSZ];
45 volatile unsigned char idata TxBuf[FSZ];
46 volatile unsigned char TxWrp, TxRdp, TxNum;
47 volatile unsigned char RxWrp, RxRdp, RxNum;
48 volatile unsigned char rec, slotn, nosync, slave, prevsample;
49 const RFConfig RxTxConf =
50 {
51 15,
52 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
53 0xaa, 0xbb, 0x12, 0x34, 0x83, 0x6f, 0x04
C51 COMPILER V8.02 WIRELESS 04/14/2006 12:17:22 PAGE 2
54 };
55 void InitBuffers(void)
56 {
57 1 RxWrp = RxRdp = RxRdp = RxNum = 0;
58 1 TxWrp = TxRdp = TxRdp = TxNum = 0;
59 1 }
60 void Delay100us(volatile unsigned char n)
61 {
62 1 unsigned char i;
63 1 while(n--)
64 1 for(i=0;i<35;i++)
65 1 ;
66 1 }
67 unsigned char SpiReadWrite(unsigned char b)
68 {
69 1 EXIF &= ~0x20; // Clear SPI interrupt
70 1 SPI_DATA = b; // Move byte to send to SPI data register
71 1 while((EXIF & 0x20) == 0x00) // Wait until SPI hs finished transmitting
72 1 ;
73 1 return SPI_DATA;
74 1 }
75 void Init(void)
76 {
77 1 unsigned char i;
78 1 P0_DIR = 0x04; // P0.2 is input, the rest output
79 1 P0 = 0x02; // P0.1 = 1 for the master/slave selection
80 1 slotn = nosync = 0;
81 1 InitBuffers();
82 1 if ((P0 & 0x04) == 0x04)
83 1 slave = 1;
84 1 else
85 1 slave = 0;
86 1 // TIMER2:
87 1 TR2 = 0; // Stop timer2 if running
88 1 CKCON |= 0x20; // T2M=1 (/4 timer clock)
89 1 RCAP2L = 0x0C; // 8KHz tick...
90 1 RCAP2H = 0xFE; // ... = 65536-16e6/(4*8e3) = FE0Ch
91 1 TF2 = 0; // Clear any pending timer2 interrupts
92 1 TR2 = 1; // Start timer2
93 1 ET2 = 1; // Enable timer2 interrupts
94 1 // PWM:
95 1 P0_ALT = 0x80; // Enable PWM output (P0.7)
96 1 PWMCON = 0xC0; // Enable 8 bit PWM, pre=min
97 1 PWMDUTY = 0xFF;
98 1 // ADC:
99 1 ADCSTATIC &= 0x1C; // DIFFM=0, SLEEP=0, CLK8=0
100 1 ADCSTATIC |= 0x03; // 12 bit
101 1 ADCCON = 0x32; // Channel 2, NPD=1, ADCRUN=0, EXTREF=1
102 1 // RADIO:
103 1 PWR_UP = 1;
104 1 Delay100us(30); // Wait > 3ms
105 1 // SPI:
106 1 SPICLK = 0x00; // Max SPICLK (=CLK/8)
107 1 SPI_CTRL = 0x02; // Connect SPI to RADIO CH1
108 1 // RADIO:
109 1 CE = 0;
110 1 CS = 1; // RF SPI CS = 1
111 1 Delay100us(0);
112 1 for(i=0;i<RxTxConf.n;i++)
113 1 {
114 2 SpiReadWrite(RxTxConf.buf[i]);
115 2 }
C51 COMPILER V8.02 WIRELESS 04/14/2006 12:17:22 PAGE 3
116 1 CS = 0;
117 1 EA = 1; // Enable global interrupts
118 1 }
119 void TxPacket(void)
120 {
121 1 unsigned char i, rp;
122 1 CE = 1;
123 1 Delay100us(0);
124 1 // All packets start with the address:
125 1 for (i=0;i<ADDR_COUNT;i++)
126 1 {
127 2 SpiReadWrite(RxTxConf.buf[ADDR_INDEX+i]);
128 2 }
129 1 /*
130 1 * Read the packet from the transmit buffer and write it to the radio with inline
131 1 * SPI commands (for increased speed) and update the buffer write pointer and
132 1 * number of bytes in buffer:
133 1 */
134 1 rp = TxRdp;
135 1 for (i=0;i<NSLOTS;i++)
136 1 {
137 2 EXIF &= ~0x20; // Clear SPI interrupt
138 2 SPI_DATA = TxBuf[rp]; // Move byte to send to SPI data register
139 2 rp++;
140 2 rp &= FMASK;
141 2 ET2 = 0;
142 2 TxNum--;
143 2 ET2 = 1;
144 2 while((EXIF & 0x20) == 0x00) // Wait until SPI hs finished transmitting
145 2 ;
146 2 }
147 1 CE = 0;
148 1 TxRdp = rp;
149 1 }
150 void RxPacket(void)
151 {
152 1 unsigned char wp;
153 1 if(slave)
154 1 {
155 2 /*
156 2 * Tell the interrupt routine that we have received
157 2 * a packet and it’s time to sync to the master:
158 2 */
159 2 ET2 = 0;
160 2 rec = 1;
161 2 nosync = 0;
162 2 ET2 = 1;
163 2 }
164 1 /*
165 1 * Read the received packet from the radio with inline SPI commands (for increased speed)
166 1 * and put it in the receive buffer and advance the buffer write pointer, and number of
167 1 * bytes in the buffer:
168 1 */
169 1 while(DR1)
170 1 {
171 2 EXIF &= ~0x20; // Clear SPI interrupt
172 2 SPI_DATA = 0; // Write dummy byte to SPI data register
173 2 wp = RxWrp;
174 2 RxWrp++;
175 2 RxWrp &= FMASK;
176 2 while((EXIF & 0x20) == 0x00) // Wait until SPI hs finished receiving
177 2 ;
C51 COMPILER V8.02 WIRELESS 04/14/2006 12:17:22 PAGE 4
178 2 RxBuf[wp] = SPI_DATA;
179 2 ET2 = 0;
180 2 RxNum++;
181 2 ET2 = 1;
182 2 }
183 1 }
184 void Timer2ISR (void) interrupt 5 using 1
185 {
186 1 unsigned char adc;
187 1 TF2 = 0; // Clear timer2 interrupt
188 1 adc = ADCDATAH; // Read ADC and...
189 1 ADCCON &= ~0x80; // ...start new...
190 1 ADCCON |= 0x80; // ...conversion
191 1 if(RxNum > 0)
192 1 {
193 2 /*
194 2 * If there are any samples in receive buffer, write next
195 2 * sample to the PWM and advance the buffer read pointer.
196 2 */
197 2 PWMDUTY = RxBuf[RxRdp];
198 2 RxRdp++;
199 2 RxRdp &= FMASK;
200 2 RxNum--;
201 2 }
202 1 TxBuf[TxWrp] = adc; // Write ADC sample to the transmit buffer and..
203 1 TxWrp++; // ..advance buffer..
204 1 TxWrp &= FMASK; // ..write pointer
205 1 TxNum++;
206 1 if(rec != 0) // Valid packet received by slave?
207 1 {
208 2 rec = 0; // Yes, preset time...
209 2 slotn = SYNCSLOT; // ...slot counter (sync to master)
210 2 } else
211 1 {
212 2 slotn++; // Increment time slot counter
213 2 if(slotn == NSLOTS) // If at beginning of frame....
214 2 {
215 3 slotn = 0; // ... reset time slot counter...
216 3 if(nosync < 255) // ...and update nosync counter
217 3 nosync++;
218 3 }
219 2 }
220 1 }
221 void SetRxMode(void)
222 {
223 1 CS = 1;
224 1 Delay100us(0);
225 1 SpiReadWrite(RxTxConf.buf[RxTxConf.n - 1] | 0x01);
226 1 CS = 0;
227 1 }
228 void SetTxMode(void)
229 {
230 1 CS = 1;
231 1 Delay100us(0);
232 1 SpiReadWrite(RxTxConf.buf[RxTxConf.n - 1]);
233 1 CS = 0;
234 1 }
235 void WaitRx(void)
236 {
237 1 SetRxMode();
238 1 CE = 1; // Radio CE = 1
239 1 while(1)
C51 COMPILER V8.02 WIRELESS 04/14/2006 12:17:22 PAGE 5
240 1 {
241 2 if(DR1) // If data ready...
242 2 {
243 3 RxPacket(); // ...receive packet
244 3 break;
245 3 }
246 2 if(slave)
247 2 {
248 3 if(nosync > NSYNC) // If slave has been out of sync for > NSYNC frames...
249 3 {
250 4 ET2 = 0;
251 4 InitBuffers(); // ...initialize buffers and continue waiting
252 4 ET2 = 1;
253 4 continue;
254 4 }
255 3 }
256 2
257 2 if(slotn >= WTSLOT)
258 2 break;
259 2 }
260 1 CE = 0;
261 1 }
262 void main(void)
263 {
264 1 Init();
265 1 if(slave)
266 1 WaitRx(); // Perform syncing if slave
267 1 while(1)
268 1 {
269 2 while(slotn != 0) // Wait until slot no. 0 (Tx)
270 2 ;
271 2 if(TxNum >= NSLOTS)
272 2 {
273 3 SetTxMode();
274 3 TxPacket();
275 3 }
276 2 while(slotn < RXSLOT)
277 2 ;
278 2 WaitRx();
279 2 }
280 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 481 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 27 1
IDATA SIZE = 64 ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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