📄 motor_master.s
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.module Motor_master.c
.area text(rom, con, rel)
.dbfile F:\IccAvr_Pro\Motor_master.c
.area data(ram, con, rel)
.dbfile F:\IccAvr_Pro\Motor_master.c
_pwm::
.blkb 2
.area idata
.byte 127,255
.area data(ram, con, rel)
.dbfile F:\IccAvr_Pro\Motor_master.c
.dbsym e pwm _pwm A[2:2]c
.area text(rom, con, rel)
.dbfile F:\IccAvr_Pro\Motor_master.c
.dbfunc e port_init _port_init fV
.even
_port_init::
.dbline -1
.dbline 19
;
; #include <iom16v.h>
; #include <macros.h>
; //#include "Display.h"
; #include "SPI_master.h"
; #include "time_master.h"
;
; extern unsigned char timeflag,dispflag;
;
;
; extern unsigned char SPI_rx_buff[SIZE];
; extern unsigned char SPI_tx_buff[SIZE];
; extern unsigned char rx_wr_index,rx_rd_index,rx_counter,rx_buffer_overflow;
; extern unsigned char tx_wr_index,tx_rd_index,tx_counter,SPI_ok,SPI_datain,temp;
;
; unsigned char pwm[2]={0x7f,0xff};
; unsigned char qep_data1[3],qep_data2[3];
; void port_init(void)
; {
.dbline 20
; PORTA = 0x00;
clr R2
out 0x1b,R2
.dbline 21
; DDRA = 0x00;
out 0x1a,R2
.dbline 22
; PORTB = 0x00;
out 0x18,R2
.dbline 23
; DDRB = 0x00;
out 0x17,R2
.dbline 24
; PORTC = 0x00; //m103 output only
out 0x15,R2
.dbline 25
; DDRC = 0x00;
out 0x14,R2
.dbline 26
; PORTD = 0x00;
out 0x12,R2
.dbline 27
; DDRD = 0x00;
out 0x11,R2
.dbline -2
L1:
.dbline 0 ; func end
ret
.dbend
.dbfunc e init_devices _init_devices fV
.even
_init_devices::
.dbline -1
.dbline 34
; }
;
;
;
; //call this routine to initialize all peripherals
; void init_devices(void)
; {
.dbline 36
; //stop errant interrupts until set up
; CLI(); //disable all interrupts
cli
.dbline 37
; port_init();
xcall _port_init
.dbline 38
; timer0_init();
xcall _timer0_init
.dbline 39
; timer2_init();
xcall _timer2_init
.dbline 40
; spi_init();
xcall _spi_init
.dbline 43
;
;
; MCUCR = 0x00;
clr R2
out 0x35,R2
.dbline 44
; GICR = 0x00;
out 0x3b,R2
.dbline 45
; TIMSK = 0x41; //timer interrupt sources
ldi R24,65
out 0x39,R24
.dbline 46
; SEI(); //re-enable interrupts
sei
.dbline -2
L2:
.dbline 0 ; func end
ret
.dbend
.dbfunc e main _main fV
; t -> R20
; set_pwm -> R10
; SPI_flag -> R20
; c -> R14
; i -> y+2
; j -> y+0
.even
_main::
sbiw R28,3
.dbline -1
.dbline 52
; //all peripherals are now initialized
; }
;
; //
; void main(void)
; {
.dbline 53
; unsigned char i=0,t=0;
clr R0
std y+2,R0
.dbline 53
clr R20
.dbline 54
; int j=0;
clr R1
std y+1,R1
std y+0,R0
.dbline 55
; unsigned char SPI_flag=1;
ldi R20,1
.dbline 57
; unsigned char c;
; unsigned char set_pwm=1;
clr R10
inc R10
.dbline 62
;
; //unsigned char aa_flag;
;
;
; init_devices();
xcall _init_devices
.dbline 64
; //insert your functional code here...
; PORTB&=~BIT(SS);
cbi 0x18,4
.dbline 65
; putSPIchar(0xaa);
ldi R16,170
xcall _putSPIchar
.dbline 66
; getSPIchar();
xcall _getSPIchar
.dbline 67
; putSPIchar(0x00);
clr R16
xcall _putSPIchar
.dbline 68
; getSPIchar();
xcall _getSPIchar
.dbline 69
; putSPIchar(0x00);
clr R16
xcall _putSPIchar
.dbline 70
; getSPIchar();
xcall _getSPIchar
.dbline 71
; putSPIchar(0x00);
clr R16
xcall _putSPIchar
.dbline 72
; getSPIchar();
xcall _getSPIchar
.dbline 73
; PORTB|=BIT(SS);
sbi 0x18,4
xjmp L5
X0:
.dbline 79
;
;
;
;
; while(1)
; {
L7:
.dbline 81
; while(timeflag)
; {
.dbline 82
; timeflag=0;
clr R2
sts _timeflag,R2
.dbline 83
; if(SPI_flag)
tst R20
brne X4
xjmp L10
X4:
.dbline 84
; {
.dbline 85
; PORTB&=~BIT(SS);
cbi 0x18,4
.dbline 86
; putSPIchar(0xaa);
ldi R16,170
xcall _putSPIchar
.dbline 87
; getSPIchar();
xcall _getSPIchar
.dbline 88
; putSPIchar(0x01);
ldi R16,1
xcall _putSPIchar
.dbline 89
; getSPIchar();
xcall _getSPIchar
.dbline 90
; putSPIchar(0x00);
clr R16
xcall _putSPIchar
.dbline 91
; for(i=0,j=-1;i<10&j<3;i++)
clr R0
std y+2,R0
ldi R24,-1
ldi R25,-1
std y+1,R25
std y+0,R24
xjmp L15
L12:
.dbline 92
; {
.dbline 93
; if((c=getSPIchar())==0x55)
xcall _getSPIchar
mov R14,R16
cpi R16,85
brne L16
.dbline 94
; j=0;
clr R0
clr R1
std y+1,R1
std y+0,R0
L16:
.dbline 95
; putSPIchar(0x44);
ldi R16,68
xcall _putSPIchar
.dbline 96
; if(j>=0)
ldd R24,y+0
ldd R25,y+1
cpi R24,0
ldi R30,0
cpc R25,R30
brlt L18
.dbline 97
; qep_data1[j++]=c;
movw R2,R24
adiw R24,1
std y+1,R25
std y+0,R24
ldi R24,<_qep_data1
ldi R25,>_qep_data1
movw R30,R2
add R30,R24
adc R31,R25
std z+0,R14
L18:
.dbline 98
L13:
.dbline 91
ldd R0,y+2
inc R0
std y+2,R0
L15:
.dbline 91
ldd R24,y+2
cpi R24,10
brsh L20
ldi R24,1
ldi R25,0
movw R12,R24
xjmp L21
L20:
clr R12
clr R13
L21:
ldd R24,y+0
ldd R25,y+1
cpi R24,3
ldi R30,0
cpc R25,R30
brge L22
ldi R22,1
ldi R23,0
xjmp L23
L22:
clr R22
clr R23
L23:
movw R2,R12
and R2,R22
and R3,R23
tst R2
breq X5
xjmp L12
X5:
tst R3
breq X6
xjmp L12
X6:
X1:
.dbline 99
; }
; getSPIchar();
xcall _getSPIchar
.dbline 101
;
; putSPIchar(0x00);
clr R16
xcall _putSPIchar
.dbline 102
; getSPIchar();
xcall _getSPIchar
.dbline 104
;
; NOP();
nop
.dbline 105
; putSPIchar(0xaa);
ldi R16,170
xcall _putSPIchar
.dbline 106
; getSPIchar();
xcall _getSPIchar
.dbline 107
; putSPIchar(0x02);
ldi R16,2
xcall _putSPIchar
.dbline 108
; getSPIchar();
xcall _getSPIchar
.dbline 109
; putSPIchar(0x00);
clr R16
xcall _putSPIchar
.dbline 110
; for(i=0,j=-1;i<10&j<3;i++)
clr R0
std y+2,R0
ldi R24,-1
ldi R25,-1
std y+1,R25
std y+0,R24
xjmp L27
L24:
.dbline 111
; {
.dbline 112
; if((c=getSPIchar())==0x56)
xcall _getSPIchar
mov R14,R16
cpi R16,86
brne L28
.dbline 113
; j=0;
clr R0
clr R1
std y+1,R1
std y+0,R0
L28:
.dbline 114
; putSPIchar(0x44);
ldi R16,68
xcall _putSPIchar
.dbline 115
; if(j>=0)
ldd R24,y+0
ldd R25,y+1
cpi R24,0
ldi R30,0
cpc R25,R30
brlt L30
.dbline 116
; qep_data2[j++]=c;
movw R2,R24
adiw R24,1
std y+1,R25
std y+0,R24
ldi R24,<_qep_data2
ldi R25,>_qep_data2
movw R30,R2
add R30,R24
adc R31,R25
std z+0,R14
L30:
.dbline 117
L25:
.dbline 110
ldd R0,y+2
inc R0
std y+2,R0
L27:
.dbline 110
ldd R24,y+2
cpi R24,10
brsh L32
ldi R22,1
ldi R23,0
xjmp L33
L32:
clr R22
clr R23
L33:
ldd R24,y+0
ldd R25,y+1
cpi R24,3
ldi R30,0
cpc R25,R30
brge L34
ldi R24,1
ldi R25,0
movw R12,R24
xjmp L35
L34:
clr R12
clr R13
L35:
movw R2,R22
and R2,R12
and R3,R13
tst R2
breq X7
xjmp L24
X7:
tst R3
breq X8
xjmp L24
X8:
X2:
.dbline 118
; }
; getSPIchar();
xcall _getSPIchar
.dbline 119
; NOP();
nop
.dbline 120
; PORTB|=BIT(SS);
sbi 0x18,4
.dbline 121
; NOP();
nop
.dbline 122
; }
L10:
.dbline 123
; if(set_pwm)
tst R10
breq L36
.dbline 124
; {
.dbline 125
; PORTB&=~BIT(SS);
cbi 0x18,4
.dbline 126
; putSPIchar(0x55);
ldi R16,85
xcall _putSPIchar
.dbline 127
; getSPIchar();
xcall _getSPIchar
.dbline 128
; putSPIchar(pwm[0]);
lds R16,_pwm
xcall _putSPIchar
.dbline 129
; getSPIchar();
xcall _getSPIchar
.dbline 130
; putSPIchar(pwm[1]);
lds R16,_pwm+1
xcall _putSPIchar
.dbline 131
; getSPIchar();
xcall _getSPIchar
.dbline 132
; putSPIchar(0x00);
clr R16
xcall _putSPIchar
.dbline 133
; getSPIchar();
xcall _getSPIchar
.dbline 134
; PORTB|=BIT(SS);
sbi 0x18,4
.dbline 135
; }
L36:
.dbline 136
L8:
.dbline 80
lds R2,_timeflag
tst R2
breq X9
xjmp L7
X9:
.dbline 137
L5:
.dbline 78
xjmp L8
X3:
.dbline -2
L3:
adiw R28,3
.dbline 0 ; func end
ret
.dbsym r t 20 c
.dbsym r set_pwm 10 c
.dbsym r SPI_flag 20 c
.dbsym r c 14 c
.dbsym l i 2 c
.dbsym l j 0 I
.dbend
.area bss(ram, con, rel)
.dbfile F:\IccAvr_Pro\Motor_master.c
_qep_data2::
.blkb 3
.dbsym e qep_data2 _qep_data2 A[3:3]c
_qep_data1::
.blkb 3
.dbsym e qep_data1 _qep_data1 A[3:3]c
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