word.vhd

Word dispaly use VHDl Langauge is ver goog

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity disp is
	port(	clk:	in std_logic;
		clka:	in std_logic;
		addr:	inout integer range 0 to 7:=0;
		data:	out std_logic_vector(7 downto 0);
		en:	out std_logic);
end;

architecture disp_arch of disp is
type romtable is array(0 to 7) of std_logic_vector(7 downto 0);
constant roma:romtable:=romtable'(
	"00010000",
	"11111110",
	"10010010",
	"11111110",
	"10010010",
	"11111110",
	"00010000",
	"00011111");

constant romb:romtable:=romtable'(
	"11111111",
	"00000010",
	"00000100",
	"11111111",
	"00001000",
	"00001000",
	"00001000",
	"00011000");

signal q: std_logic_vector (3 downto 0);

begin
	en<='0';

	process(clka)
	begin
		if rising_edge(clka) then
			q<=q+'1';
		end if;
	end process;

	process(clk)
	begin
	if rising_edge(clk) then
		if addr=7 then
			addr<=0;
		else
			addr<=addr+1;
		end if;
	end if;
	end process;

	process(addr)
	begin
		if q(3)='1' then 
			data<=roma(addr);
		else
			data<=romb(addr);
		end if;
	end process;

end disp_arch;