main.c

This zip describes how two SSCs in I2S mode play and record wave files through a two-input data meth

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : main.c
//* Object              : basic I2S application for Read and Write
//* Creation            : JPP 23/May/2003 
//* Modification: JPP 23/May/2003 bug setting AT91C_SSC1_RFMR in 2 ssc mode change 31 by 16
//*----------------------------------------------------------------------------
#include "main.h"


//* ====================== External function prototyping ======================
extern void debug_message(void);
extern void menu(char value);

//* =========================== Global Data prototyping =======================
int pool;
volatile unsigned int data_out;
volatile unsigned int data_out0;
volatile unsigned int data_in[2];

AT91PS_SSC	pSSC = AT91C_BASE_SSC1;

//* ========================== Internal define  ===============================

#define MCK	60000000
#define FILE_SAMPLING_FREQ	44100 // in Hz

// Constant declarations used by I2S mode
#define SLOT_BY_FRAME	2
#define BITS_BY_SLOT	16
// IRQ level declaration
#define IRQ_LEVEL_I2S	5	

// SSC_TCMR  configuration for I2S setting
// I2S_ASY_MASTER_TX_SETTING(BITS_BY_SLOT, SLOT_BY_FRAME);
#define I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
AT91C_SSC_CKS_DIV   +\
AT91C_SSC_CKO_CONTINOUS      +\
AT91C_SSC_START_FALL_RF +\
((1<<16) & AT91C_SSC_STTDLY) +\
((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))

//AT91C_SSC_STTOUT  +\  with out no work FOR VERSION BEFORE Rev F
//AT91C_SSC_CKG_NONE    +\

//* Configuration to set in the SSC_TFMR Transmit Frame Mode Register
//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
//* 			 nb_slot_by_frame : number of channels
#define I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
(nb_bit_by_slot-1)  +\
AT91C_SSC_MSBF   +\
(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
AT91C_SSC_FSOS_NEGATIVE)


//*--------------------------------------------------------------------------------------
//* Function Name       : stand_I2S_done
//* Object              : Standart I2S out using Interrupt and PDC transmission 
//* Input Parameters    : none. 
//* Output Parameters   : none.
//*--------------------------------------------------------------------------------------
void stand_I2S_done(void)
{
    // ============================= Init SSC1 in Output mode =============================
	//* Configure SSC1 PIOs  TF/TK/TD  
	*AT91C_PIOB_PDR=    ((unsigned int) AT91C_PB7_TK1 ) |
	                    ((unsigned int) AT91C_PB8_TD1 ) |
	                    ((unsigned int) AT91C_PB6_TF1 );
    
    //* Configure PMC by enabling SSC1 clock    
	AT91F_SSC1_CfgPMC(); 
    //* Reset All the Peripheral 
	pSSC->SSC_CR = AT91C_SSC_SWRST ;

    //* Clear Transmit and Receive Counters
	AT91F_PDC_Close((AT91PS_PDC) &(pSSC->SSC_RPR));

    //* Define the Clock Mode Register at 2*16*44100 => 1.4112 MHz
	AT91F_SSC_SetBaudrate(pSSC, MCK, FILE_SAMPLING_FREQ*(BITS_BY_SLOT*SLOT_BY_FRAME));

    //* Write the Transmit Frame Mode Register
	pSSC->SSC_TFMR =  I2S_ASY_TX_FRAME_SETTING(BITS_BY_SLOT, SLOT_BY_FRAME);

    //* Configure AIC controller to handle SSC interrupts
	AT91F_AIC_ConfigureIt (
		AT91C_BASE_AIC,                        // AIC base address
		AT91C_ID_SSC1,                         // System peripheral ID
		IRQ_LEVEL_I2S,                         // Max priority
		AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, // Level sensitive
		AT91F_ASM_I2S_Handler );
    //* Enable SSC interrupt in AIC
	AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SSC1);

    //* PDC configuration
	AT91F_PDC_SetTx ((AT91PS_PDC) &(pSSC->SSC_RPR),		// PDC SSC base address	
					 (char *)wav_file,	// pointer to data
					 AT91C_WAV_FILE_SIZE/2);// Number of 16 bits words
	AT91F_PDC_SetNextTx ((AT91PS_PDC) &(pSSC->SSC_RPR),	// PDC SSC base address
				         (char *)wav_file, 	// pointer to next data
				         AT91C_WAV_FILE_SIZE/2);// Number of 16 bits words
						 
    //* SSC Enable Interrupt 
	AT91F_SSC_EnableIt (pSSC, AT91C_SSC_ENDTX);
    //* Enable PDC feature
	AT91F_PDC_EnableTx ((AT91PS_PDC) &(pSSC->SSC_RPR));	

    //* Enable Transmit AND Start music !!!
        //* Write the Transmit Clock Mode Register and Enable TK and TF
	pSSC->SSC_TCMR =  I2S_ASY_MASTER_TX_SETTING(BITS_BY_SLOT, SLOT_BY_FRAME);
	//* Enable TX
	AT91F_SSC_EnableTx (pSSC);

}


//*--------------------------------------------------------------------------------------
//* Function Name       : polling
//* Object              : Use I2S in polling mode for debug only
//* Input Parameters    : none. 
//* Output Parameters   : none.
//*--------------------------------------------------------------------------------------
void polling(void)
{
    // ============================= Init SSC1 in Output mode =============================
	//* Configure SSC1 PIOs  TF/TK/TD  
	*AT91C_PIOB_PDR= ((unsigned int) AT91C_PB7_TK1     ) |
			 ((unsigned int) AT91C_PB8_TD1     ) |
			 ((unsigned int) AT91C_PB6_TF1     );

    //* Configure PMC by enabling SSC1 clock  
       	*AT91C_PMC_PCER |= 1 << AT91C_ID_SSC1;    /* enable the SSC1 peripheral clock */
    //* Reset All the Peripheral 
     	*AT91C_SSC1_CR = AT91C_SSC_SWRST ;
    //* Clear Transmit and Receive Counters
	AT91F_PDC_Close((AT91PS_PDC) &(pSSC->SSC_RPR));
    //* Define the Clock Mode Register
    // for MCK ei 60000000 => 21 
        *AT91C_SSC1_CMR = 0x15;        
  
    //* Write the Transmit Frame Mode Register
        *AT91C_SSC1_TCMR =  ((((BITS_BY_SLOT*SLOT_BY_FRAME)/2) -1) <<24) |
   		   ((1<<16) & AT91C_SSC_STTDLY) |
		   AT91C_SSC_START_FALL_RF | 
		   AT91C_SSC_CKO_CONTINOUS | 	// continuous transmit clock
		   AT91C_SSC_CKS_DIV; 		// Divided clock
     //set AT91C_SSC_STTOUT in TCMT +\  with out no work FOR VERSION BEFORE Rev F

     *AT91C_SSC1_TFMR =  
     		AT91C_SSC_FSOS_NEGATIVE 	|
		(((BITS_BY_SLOT-1)<<16) & AT91C_SSC_FSLEN)  |   // Fslen => 16 Clock
		(((SLOT_BY_FRAME-1)<<8) & AT91C_SSC_DATNB) |   // 2 Word by frame
		 AT91C_SSC_MSBF	    		|	// MSB in first
		 (BITS_BY_SLOT-1) ;		// 16 bits
	//* Enable TX
	*AT91C_SSC1_CR = AT91C_SSC_TXEN;    /* Enable Tx */
	
data_out= 0x8002;	
data_out0= 0x4001;	
	pool =1;
}

//*--------------------------------------------------------------------------------------
//* Function Name       : I2S_mode_output32Bit_Input31Bits
//* Object              : Write 2 data and read 1 data in I2S When the data is read need 
//*			 shift operation 
//*			  for 
//* Input Parameters    : none. 
//* Output Parameters   : none.
//*--------------------------------------------------------------------------------------
void I2S_mode_output32Bit_Input31Bits(void)
{
    char value;
    // ========================= Init SSC1 in Input Output mode ==========================
    //* Configure SSC1 PIOs  TF/TK/TD  & RD and must loop RD/TD with wire 
	*AT91C_PIOB_PDR= ((unsigned int) AT91C_PB9_RD1     ) |
			 ((unsigned int) AT91C_PB7_TK1     ) |
			 ((unsigned int) AT91C_PB8_TD1     ) |
			 ((unsigned int) AT91C_PB6_TF1     );
    //* Configure PMC by enabling SSC1 clock  
       	*AT91C_PMC_PCER |= 1 << AT91C_ID_SSC1;    /* enable the SSC1 peripheral clock */
    //* Reset All the Peripheral 
     	*AT91C_SSC1_CR = AT91C_SSC_SWRST ;
    //* Clear Transmit and Receive Counters
	AT91F_PDC_Close((AT91PS_PDC) &(pSSC->SSC_RPR));
    //* Define the Clock Mode Register
    // for MCK ei 60000000 => 21 
        *AT91C_SSC1_CMR = 21;        

    //* Write the Recivier Frame Mode Register
	*AT91C_SSC1_RCMR = AT91C_SSC_CKS_TK |   // Use TK clock
   		((1<<16) & AT91C_SSC_STTDLY)|
		          0x1 << 8          |   // Start ON TX
		           AT91C_SSC_CKI    |   // Rissing edge
		          AT91C_SSC_START_TX; 

	*AT91C_SSC1_RFMR = 
		  ((1-1) <<8) & AT91C_SSC_DATNB |        // 1 Word by frame
                                 AT91C_SSC_MSBF |
				 (31-1);		 // 31 bits
    //* Write the Transmit Frame Mode Register
        *AT91C_SSC1_TCMR =  ((((BITS_BY_SLOT*SLOT_BY_FRAME)/2) -1) <<24) |
   		   ((1<<16) & AT91C_SSC_STTDLY) |
		   AT91C_SSC_START_FALL_RF | 
		   AT91C_SSC_CKO_CONTINOUS | 	// continuous transmit clock
		   AT91C_SSC_CKS_DIV; 		// Divided clock
    //set AT91C_SSC_STTOUT in TCMT +\  with out no work FOR VERSION BEFORE Rev F
        *AT91C_SSC1_TFMR =  
     		AT91C_SSC_FSOS_NEGATIVE 	|
		(((BITS_BY_SLOT-1)<<16) & AT91C_SSC_FSLEN)  |   // Fslen => 16 Clock
		(((SLOT_BY_FRAME-1)<<8) & AT91C_SSC_DATNB) |   // 2 Word by frame
		 AT91C_SSC_MSBF	    		|	// MSB in first
		 (BITS_BY_SLOT-1) ;		// 16 bits

	//* Enable TX & RX
	*AT91C_SSC1_CR = AT91C_SSC_TXEN | AT91C_SSC_RXEN;    /* Enable Tx */

	data_out= 0xAAAF;
	data_out0= 0xF0F1;
	pool =1;
	while (1)
	{