irq_ghs.mac

This zip describes how two SSCs in I2S mode play and record wave files through a two-input data meth

;------------------------------------------------------------------------------
;-    ATMEL Microcontroller Software Support  -   ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;------------------------------------------------------------------------------
;- File source          : irq_ghs.mac
;- Object               : Entry and Exit Macro for IRQ and FIQ.
;-
;- 1.0 01/04/00 JCZ     : Creation
;- 1.1 02/11/00 JPP     : Green Hills
;- 1.2 10/10/02 JPP     : Update FIQ and IRQ management to reduce interrupt cycle
;-                        You can also win in the standard Cstartup
;-IRQ_STACK_SIZE      EQU     (3*8*4)     ; 3 words per interrupt priority level
;-FIQ_STACK_SIZE      EQU     (3*4)       ; 3 words
;- Can be changed by
;-IRQ_STACK_SIZE      EQU     (2*8*4)     ; 2 words per interrupt priority level
;-FIQ_STACK_SIZE      EQU     (0*4)       ; 0 words
;------------------------------------------------------------------------------

;--------------------------------
;- ARM Core Mode and Status Bits
;--------------------------------

ARM_MODE_USER           EQU     0x10
ARM_MODE_FIQ            EQU     0x11
ARM_MODE_IRQ            EQU     0x12
ARM_MODE_SVC            EQU     0x13
ARM_MODE_ABORT          EQU     0x17
ARM_MODE_UNDEF          EQU     0x1B
ARM_MODE_SYS            EQU     0x1F

I_BIT                   EQU     0x80
F_BIT                   EQU     0x40
T_BIT                   EQU     0x20


;- IRQ Entry
;- Register initialization
;-      Banked Registers        ; Irq_register
;-      SPSR need to be saved for nested interrupt
;-      R13_irq <- Irq Stack register
;-      R14_irq <- Irq link register
;-----------
            .macro      IRQ_ENTRY

;- Adjust and save LR_irq in IRQ stack
            sub         lr, lr, #4
            stmfd       sp!, {lr}

;- Write in the IVR to support Protect Mode
;- No effect in Normal Mode
;- De-assert the NIRQ and clear the source in Protect Mode
            ldr         r14, =AT91C_BASE_AIC
            str         r14, [r14, #AIC_IVR]

;- Save SPSR and r0 in IRQ stack
            mrs         r14, SPSR
            stmfd       sp!, {r14}

;- Enable Interrupt and Switch in Supervisor Mode
           msr         CPSR_c, #ARM_MODE_SYS

;- Save scratch/used registers and LR in User Stack
            stmfd       sp!, { r0-r3, r12, r14}

            .endm

;- IRQ Exit
;-----------
            .macro      IRQ_EXIT
;- Restore scratch/used registers and LR from User Stack
            ldmia       sp!, { r0-r3, r12, r14}

;- Disable Interrupt and switch back in IRQ mode
            msr         CPSR_c, #I_BIT | ARM_MODE_IRQ

;- Mark the End of Interrupt on the AIC
            ldr         r14, =AT91C_BASE_AIC
            str         r14, [r14, #AIC_EOICR]

;- Restore SPSR_irq and r0 from IRQ stack
            ldmia       sp!, {r14}
            msr         SPSR_cxsf, r14

;- Restore adjusted  LR_irq from IRQ stack directly in the PC
            ldmia       sp!, {pc}^

            .endm

;-------------------
;- FIQ Entry Macro -
;-------------------
;- FIQ Entry with no nested (reentrant) interrupt allowed.
;- Register initialization
;-      Banked Registers        ; FIQ_register
;-      SPSR does not need to be save because we do not want nested FIQ
;-      R13_fiq <- Same as above. No need to save it.
;-      R14_irq <- link register
;------------------------------------------------------------------------

            .macro      FIQ_ENTRY

;- Switch in SYS/User Mode to allow User Stack access for C code and Disable FIQ and IRQ Interrupt for this mode
; because the FIQ is not yet acknowledged

            msr         CPSR_c,#I_BIT | F_BIT | #ARM_MODE_SVC

;- Save scratch/used registers and LR in User Stack
            stmfd       sp!, { r0-r3, r12, lr}
            .endm

;------------
;- FIQ Exit -
;------------
            .macro      FIQ_EXIT

;- Restore scratch/used registers and LR from User Stack
            ldmia       sp!, { r0-r3, r12, lr}

;- Leave Interrupts disabled and switch back in FIQ mode
            msr         CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ

;- Restore the Program Counter using the LR_fiq directly in the PC
            subs        pc,lr,#4
            .endm