io_map.c

ucos-ii for hc12 in codewarrior

volatile PTITSTR _PTIT @(REG_BASE + 0x00000201);           /* Port T Input Register; 0x00000201 */
volatile DDRTSTR _DDRT @(REG_BASE + 0x00000202);           /* Port T Data Direction Register; 0x00000202 */
volatile RDRTSTR _RDRT @(REG_BASE + 0x00000203);           /* Port T Reduced Drive Register; 0x00000203 */
volatile PERTSTR _PERT @(REG_BASE + 0x00000204);           /* Port T Pull Device Enable Register; 0x00000204 */
volatile PPSTSTR _PPST @(REG_BASE + 0x00000205);           /* Port T Polarity Select Register; 0x00000205 */
volatile PTSSTR _PTS @(REG_BASE + 0x00000208);             /* Port S I/O Register; 0x00000208 */
volatile PTISSTR _PTIS @(REG_BASE + 0x00000209);           /* Port S Input Register; 0x00000209 */
volatile DDRSSTR _DDRS @(REG_BASE + 0x0000020A);           /* Port S Data Direction Register; 0x0000020A */
volatile RDRSSTR _RDRS @(REG_BASE + 0x0000020B);           /* Port S Reduced Drive Register; 0x0000020B */
volatile PERSSTR _PERS @(REG_BASE + 0x0000020C);           /* Port S Pull Device Enable Register; 0x0000020C */
volatile PPSSSTR _PPSS @(REG_BASE + 0x0000020D);           /* Port S Polarity Select Register; 0x0000020D */
volatile WOMSSTR _WOMS @(REG_BASE + 0x0000020E);           /* Port S Wired-Or Mode Register; 0x0000020E */
volatile PTMSTR _PTM @(REG_BASE + 0x00000210);             /* Port M I/O Register; 0x00000210 */
volatile PTIMSTR _PTIM @(REG_BASE + 0x00000211);           /* Port M Input Register; 0x00000211 */
volatile DDRMSTR _DDRM @(REG_BASE + 0x00000212);           /* Port M Data Direction Register; 0x00000212 */
volatile RDRMSTR _RDRM @(REG_BASE + 0x00000213);           /* Port M Reduced Drive Register; 0x00000213 */
volatile PERMSTR _PERM @(REG_BASE + 0x00000214);           /* Port M Pull Device Enable Register; 0x00000214 */
volatile PPSMSTR _PPSM @(REG_BASE + 0x00000215);           /* Port M Polarity Select Register; 0x00000215 */
volatile WOMMSTR _WOMM @(REG_BASE + 0x00000216);           /* Port M Wired-Or Mode Register; 0x00000216 */
volatile PTPSTR _PTP @(REG_BASE + 0x00000218);             /* Port P I/O Register; 0x00000218 */
volatile PTIPSTR _PTIP @(REG_BASE + 0x00000219);           /* Port P Input Register; 0x00000219 */
volatile DDRPSTR _DDRP @(REG_BASE + 0x0000021A);           /* Port P Data Direction Register; 0x0000021A */
volatile RDRPSTR _RDRP @(REG_BASE + 0x0000021B);           /* Port P Reduced Drive Register; 0x0000021B */
volatile PERPSTR _PERP @(REG_BASE + 0x0000021C);           /* Port P Pull Device Enable Register; 0x0000021C */
volatile PPSPSTR _PPSP @(REG_BASE + 0x0000021D);           /* Port P Polarity Select Register; 0x0000021D */
volatile PTHSTR _PTH @(REG_BASE + 0x00000220);             /* Port H I/O Register; 0x00000220 */
volatile PTIHSTR _PTIH @(REG_BASE + 0x00000221);           /* Port H Input Register; 0x00000221 */
volatile DDRHSTR _DDRH @(REG_BASE + 0x00000222);           /* Port H Data Direction Register; 0x00000222 */
volatile RDRHSTR _RDRH @(REG_BASE + 0x00000223);           /* Port H Reduced Drive Register; 0x00000223 */
volatile PERHSTR _PERH @(REG_BASE + 0x00000224);           /* Port H Pull Device Enable Register; 0x00000224 */
volatile PPSHSTR _PPSH @(REG_BASE + 0x00000225);           /* Port H Polarity Select Register; 0x00000225 */
volatile PIEHSTR _PIEH @(REG_BASE + 0x00000226);           /* Port H Interrupt Enable Register; 0x00000226 */
volatile PIFHSTR _PIFH @(REG_BASE + 0x00000227);           /* Port H Interrupt Flag Register; 0x00000227 */
volatile PTJSTR _PTJ @(REG_BASE + 0x00000228);             /* Port J I/O Register; 0x00000228 */
volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000229);           /* Port J Input Register; 0x00000229 */
volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000022A);           /* Port J Data Direction Register; 0x0000022A */
volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000022B);           /* Port J Reduced Drive Register; 0x0000022B */
volatile PERJSTR _PERJ @(REG_BASE + 0x0000022C);           /* Port J Pull Device Enable Register; 0x0000022C */
volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000022D);           /* Port J Polarity Select Register; 0x0000022D */
volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000022E);           /* Port J Interrupt Enable Register; 0x0000022E */
volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000022F);           /* Port J Interrupt Flag Register; 0x0000022F */
volatile PTLSTR _PTL @(REG_BASE + 0x00000230);             /* Port L I/O Register; 0x00000230 */
volatile PTILSTR _PTIL @(REG_BASE + 0x00000231);           /* Port L Input Register; 0x00000231 */
volatile DDRLSTR _DDRL @(REG_BASE + 0x00000232);           /* Port L Data Direction Register; 0x00000232 */
volatile RDRLSTR _RDRL @(REG_BASE + 0x00000233);           /* Port L Reduced Drive Register; 0x00000233 */
volatile PERLSTR _PERL @(REG_BASE + 0x00000234);           /* Port L Pull Device Enable Register; 0x00000234 */
volatile PPSLSTR _PPSL @(REG_BASE + 0x00000235);           /* Port L Polarity Select Register; 0x00000235 */
volatile PTUSTR _PTU @(REG_BASE + 0x00000238);             /* Port U I/O Register; 0x00000238 */
volatile PTIUSTR _PTIU @(REG_BASE + 0x00000239);           /* Port U Input Register; 0x00000239 */
volatile DDRUSTR _DDRU @(REG_BASE + 0x0000023A);           /* Port U Data Direction Register; 0x0000023A */
volatile SRRUSTR _SRRU @(REG_BASE + 0x0000023B);           /* Port U Slew Rate Register; 0x0000023B */
volatile PERUSTR _PERU @(REG_BASE + 0x0000023C);           /* Port U Pull Device Enable Register; 0x0000023C */
volatile PPSUSTR _PPSU @(REG_BASE + 0x0000023D);           /* Port U Polarity Select Register; 0x0000023D */
volatile PTVSTR _PTV @(REG_BASE + 0x00000240);             /* Port V I/O Register; 0x00000240 */
volatile PTIVSTR _PTIV @(REG_BASE + 0x00000241);           /* Port V Input Register; 0x00000241 */
volatile DDRVSTR _DDRV @(REG_BASE + 0x00000242);           /* Port V Data Direction Register; 0x00000242 */
volatile SRRVSTR _SRRV @(REG_BASE + 0x00000243);           /* Port V Reduced Drive Register; 0x00000243 */
volatile PERVSTR _PERV @(REG_BASE + 0x00000244);           /* Port V Pull Device Enable Register; 0x00000244 */
volatile PPSVSTR _PPSV @(REG_BASE + 0x00000245);           /* Port V Polarity Select Register; 0x00000245 */
volatile PTWSTR _PTW @(REG_BASE + 0x00000248);             /* Port W I/O Register; 0x00000248 */
volatile PTIWSTR _PTIW @(REG_BASE + 0x00000249);           /* Port W Input Register; 0x00000249 */
volatile DDRWSTR _DDRW @(REG_BASE + 0x0000024A);           /* Port W Data Direction Register; 0x0000024A */
volatile SRRWSTR _SRRW @(REG_BASE + 0x0000024B);           /* Port W Reduced Drive Register; 0x0000024B */
volatile PERWSTR _PERW @(REG_BASE + 0x0000024C);           /* Port W Pull Device Enable Register; 0x0000024C */
volatile PPSWSTR _PPSW @(REG_BASE + 0x0000024D);           /* Port W Polarity Select Register; 0x0000024D */


/* * * * *  16-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);       /* Port AB Register; 0x00000000 */
volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);         /* Port AB Data Direction Register; 0x00000002 */
volatile PARTIDSTR _PARTID @(REG_BASE + 0x0000001A);       /* Part ID Register; 0x0000001A */
volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);           /* Timer Count Register; 0x00000044 */
volatile TC0STR _TC0 @(REG_BASE + 0x00000050);             /* Timer Input Capture/Output Compare Register 0; 0x00000050 */
volatile TC1STR _TC1 @(REG_BASE + 0x00000052);             /* Timer Input Capture/Output Compare Register 1; 0x00000052 */
volatile TC2STR _TC2 @(REG_BASE + 0x00000054);             /* Timer Input Capture/Output Compare Register 2; 0x00000054 */
volatile TC3STR _TC3 @(REG_BASE + 0x00000056);             /* Timer Input Capture/Output Compare Register 3; 0x00000056 */
volatile TC4STR _TC4 @(REG_BASE + 0x00000058);             /* Timer Input Capture/Output Compare Register 4; 0x00000058 */
volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);             /* Timer Input Capture/Output Compare Register 5; 0x0000005A */
volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);             /* Timer Input Capture/Output Compare Register 6; 0x0000005C */
volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);             /* Timer Input Capture/Output Compare Register 7; 0x0000005E */
volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062);         /* Pulse Accumulators Count Register; 0x00000062 */
volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082);   /* ATD Control Register 23; 0x00000082 */
volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084);   /* ATD Control Register 45; 0x00000084 */
volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008C);     /* ATD Input Enable Register; 0x0000008C */
volatile PORTADSTR _PORTAD @(REG_BASE + 0x0000008E);       /* Port AD0 Data; 0x0000008E */
volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090);       /* ATD Conversion Result Register 0; 0x00000090 */
volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092);       /* ATD Conversion Result Register 1; 0x00000092 */
volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094);       /* ATD Conversion Result Register 2; 0x00000094 */
volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096);       /* ATD Conversion Result Register 3; 0x00000096 */
volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098);       /* ATD Conversion Result Register 4; 0x00000098 */
volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A);       /* ATD Conversion Result Register 5; 0x0000009A */
volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C);       /* ATD Conversion Result Register 6; 0x0000009C */
volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E);       /* ATD Conversion Result Register 7; 0x0000009E */
volatile ATDDR8STR _ATDDR8 @(REG_BASE + 0x000000A0);       /* ATD Conversion Result Register 8; 0x000000A0 */
volatile ATDDR9STR _ATDDR9 @(REG_BASE + 0x000000A2);       /* ATD Conversion Result Register 9; 0x000000A2 */
volatile ATDDR10STR _ATDDR10 @(REG_BASE + 0x000000A4);     /* ATD Conversion Result Register 10; 0x000000A4 */
volatile ATDDR11STR _ATDDR11 @(REG_BASE + 0x000000A6);     /* ATD Conversion Result Register 11; 0x000000A6 */
volatile ATDDR12STR _ATDDR12 @(REG_BASE + 0x000000A8);     /* ATD Conversion Result Register 12; 0x000000A8 */
volatile ATDDR13STR _ATDDR13 @(REG_BASE + 0x000000AA);     /* ATD Conversion Result Register 13; 0x000000AA */
volatile ATDDR14STR _ATDDR14 @(REG_BASE + 0x000000AC);     /* ATD Conversion Result Register 14; 0x000000AC */
volatile ATDDR15STR _ATDDR15 @(REG_BASE + 0x000000AE);     /* ATD Conversion Result Register 15; 0x000000AE */
volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8);       /* SCI 0 Baud Rate Register; 0x000000C8 */
volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0);       /* SCI 1 Baud Rate Register; 0x000000D0 */
volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC);   /* PWM Channel Counter 01 Register; 0x000000EC */
volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE);   /* PWM Channel Counter 23 Register; 0x000000EE */
volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0);   /* PWM Channel Counter 45 Register; 0x000000F0 */
volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2);   /* PWM Channel Period 01 Register; 0x000000F2 */
volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4);   /* PWM Channel Period 23 Register; 0x000000F4 */
volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6);   /* PWM Channel Period 45 Register; 0x000000F6 */
volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8);   /* PWM Channel Duty 01 Register; 0x000000F8 */
volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA);   /* PWM Channel Duty 23 Register; 0x000000FA */
volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC);   /* PWM Channel Duty 45 Register; 0x000000FC */
volatile CAN0RXTSRSTR _CAN0RXTSR @(REG_BASE + 0x0000016E); /* MSCAN 0 Receive Time Stamp Register; 0x0000016E */
volatile CAN0TXTSRSTR _CAN0TXTSR @(REG_BASE + 0x0000017E); /* MSCAN 0 Transmit Time Stamp Register; 0x0000017E */
volatile CAN1RXTSRSTR _CAN1RXTSR @(REG_BASE + 0x000001AE); /* MSCAN 1 Receive Time Stamp Register; 0x000001AE */
volatile CAN1TXTSRSTR _CAN1TXTSR @(REG_BASE + 0x000001BE); /* MSCAN 1 Transmit Time Stamp Register; 0x000001BE */
volatile MCPERSTR _MCPER @(REG_BASE + 0x000001C2);         /* Motor Controller Period Register, with DITH = 0; 0x000001C2 */
volatile MCDC0STR _MCDC0 @(REG_BASE + 0x000001E0);         /* Motor Controller Duty Cycle Register 0; 0x000001E0 */
volatile MCDC1STR _MCDC1 @(REG_BASE + 0x000001E2);         /* Motor Controller Duty Cycle Register 1; 0x000001E2 */
volatile MCDC2STR _MCDC2 @(REG_BASE + 0x000001E4);         /* Motor Controller Duty Cycle Register 2; 0x000001E4 */
volatile MCDC3STR _MCDC3 @(REG_BASE + 0x000001E6);         /* Motor Controller Duty Cycle Register 3; 0x000001E6 */
volatile MCDC4STR _MCDC4 @(REG_BASE + 0x000001E8);         /* Motor Controller Duty Cycle Register 4; 0x000001E8 */
volatile MCDC5STR _MCDC5 @(REG_BASE + 0x000001EA);         /* Motor Controller Duty Cycle Register 5; 0x000001EA */
volatile MCDC6STR _MCDC6 @(REG_BASE + 0x000001EC);         /* Motor Controller Duty Cycle Register 6; 0x000001EC */
volatile MCDC7STR _MCDC7 @(REG_BASE + 0x000001EE);         /* Motor Controller Duty Cycle Register 7; 0x000001EE */
volatile MCDC8STR _MCDC8 @(REG_BASE + 0x000001F0);         /* Motor Controller Duty Cycle Register 8; 0x000001F0 */
volatile MCDC9STR _MCDC9 @(REG_BASE + 0x000001F2);         /* Motor Controller Duty Cycle Register 9; 0x000001F2 */
volatile MCDC10STR _MCDC10 @(REG_BASE + 0x000001F4);       /* Motor Controller Duty Cycle Register 10; 0x000001F4 */
volatile MCDC11STR _MCDC11 @(REG_BASE + 0x000001F6);       /* Motor Controller Duty Cycle Register 11; 0x000001F6 */

/* EOF */
/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 2.95 [03.62]
**     for the Freescale HCS12 series of microcontrollers.
**
** ###################################################################
*/