io_map.c

ucos-ii for hc12 in codewarrior

/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : IO_Map.C
**     Project   : _2006_01_02_PE
**     Processor : MC9S12H256CPV
**     Beantype  : IO_Map
**     Version   : Driver 01.03
**     Compiler  : Metrowerks HC12 C Compiler
**     Date/Time : 1/3/2006, 3:21 PM
**     Abstract  :
**         IO_Map.h - implements an IO device's mapping. 
**         This module contains symbol definitions of all peripheral 
**         registers and bits. 
**     Settings  :
**
**     Contents  :
**         No public methods
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2004
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : [e-mail]
** ###################################################################*/
/* Based on CPU DB MC9S12H256_112, version 2.87.329 (RegistersPrg V1.097) */
/* DataSheet : 9S12H256BDGV1/D V01.16 */

#include "PE_types.h"
#include "IO_Map.h"


/* * * * *  8-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);         /* Port E Register; 0x00000008 */
volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);           /* Port E Data Direction Register; 0x00000009 */
volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);           /* Port E Assignment Register; 0x0000000A */
volatile MODESTR _MODE @(REG_BASE + 0x0000000B);           /* Mode Register; 0x0000000B */
volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);           /* Pull-Up Control Register; 0x0000000C */
volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);         /* Reduced Drive of I/O Lines; 0x0000000D */
volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);       /* External Bus Interface Control; 0x0000000E */
volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);       /* Initialization of Internal RAM Position Register; 0x00000010 */
volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);       /* Initialization of Internal Registers Position Register; 0x00000011 */
volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);       /* Initialization of Internal EEPROM Position Register; 0x00000012 */
volatile MISCSTR _MISC @(REG_BASE + 0x00000013);           /* Miscellaneous System Control Register; 0x00000013 */
volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);           /* Interrupt Test Control Register; 0x00000015 */
volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);         /* Interrupt Test Register; 0x00000016 */
volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);     /* Memory Size Register Zero; 0x0000001C */
volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);     /* Memory Size Register One; 0x0000001D */
volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);         /* Interrupt Control Register; 0x0000001E */
volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);         /* Highest Priority I Interrupt; 0x0000001F */
volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);       /* Breakpoint Control Register 0; 0x00000028 */
volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);       /* Breakpoint Control Register 1; 0x00000029 */
volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);         /* First Address Memory Expansion Breakpoint Register; 0x0000002A */
volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);         /* First Address High Byte Breakpoint Register; 0x0000002B */
volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);         /* First Address Low Byte Breakpoint Register; 0x0000002C */
volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);         /* Second Address Memory Expansion Breakpoint Register; 0x0000002D */
volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);         /* Data (Second Address) High Byte Breakpoint Register; 0x0000002E */
volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);         /* Data (Second Address) Low Byte Breakpoint Register; 0x0000002F */
volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);         /* Page Index Register; 0x00000030 */
volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);         /* Port K Data Register; 0x00000032 */
volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);           /* Port K Data Direction Register; 0x00000033 */
volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);           /* CRG Synthesizer Register; 0x00000034 */
volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);         /* CRG Reference Divider Register; 0x00000035 */
volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);       /* CRG Flags Register; 0x00000037 */
volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);       /* CRG Interrupt Enable Register; 0x00000038 */
volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);       /* CRG Clock Select Register; 0x00000039 */
volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);       /* CRG PLL Control Register; 0x0000003A */
volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);       /* CRG RTI Control Register; 0x0000003B */
volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);       /* CRG COP Control Register; 0x0000003C */
volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);       /* CRG COP Timer Arm/Reset Register; 0x0000003F */
volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);           /* Timer Input Capture/Output Compare Select; 0x00000040 */
volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);         /* Timer Compare Force Register; 0x00000041 */
volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);           /* Output Compare 7 Mask Register; 0x00000042 */
volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);           /* Output Compare 7 Data Register; 0x00000043 */
volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);         /* Timer System Control Register1; 0x00000046 */
volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);           /* Timer Toggle On Overflow Register; 0x00000047 */
volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);         /* Timer Control Register 1; 0x00000048 */
volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);         /* Timer Control Register 2; 0x00000049 */
volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);         /* Timer Control Register 3; 0x0000004A */
volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);         /* Timer Control Register 4; 0x0000004B */
volatile TIESTR _TIE @(REG_BASE + 0x0000004C);             /* Timer Interrupt Enable Register; 0x0000004C */
volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);         /* Timer System Control Register 2; 0x0000004D */
volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);         /* Main Timer Interrupt Flag 1; 0x0000004E */
volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);         /* Main Timer Interrupt Flag 2; 0x0000004F */
volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);         /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */
volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);         /* Pulse Accumulator A Flag Register; 0x00000061 */
volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086);   /* ATD Status Register 0; 0x00000086 */
volatile ATDTEST1STR _ATDTEST1 @(REG_BASE + 0x00000089);   /* ATD Test Register; 0x00000089 */
volatile ATDSTAT2STR _ATDSTAT2 @(REG_BASE + 0x0000008A);   /* ATD Status Register 2; 0x0000008A */
volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B);   /* ATD Status Register 1; 0x0000008B */
volatile IBADSTR _IBAD @(REG_BASE + 0x000000C0);           /* IIC Address Register; 0x000000C0 */
volatile IBFDSTR _IBFD @(REG_BASE + 0x000000C1);           /* IIC Frequency Divider Register; 0x000000C1 */
volatile IBCRSTR _IBCR @(REG_BASE + 0x000000C2);           /* IIC Control Register; 0x000000C2 */
volatile IBSRSTR _IBSR @(REG_BASE + 0x000000C3);           /* IIC Status Register; 0x000000C3 */
volatile IBDRSTR _IBDR @(REG_BASE + 0x000000C4);           /* IIC Data I/O Register; 0x000000C4 */
volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA);     /* SCI 0 Control Register 1; 0x000000CA */
volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB);     /* SCI 0 Control Register 2; 0x000000CB */
volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC);     /* SCI 0 Status Register 1; 0x000000CC */
volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD);     /* SCI 0 Status Register 2; 0x000000CD */
volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE);     /* SCI 0 Data Register High; 0x000000CE */
volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF);     /* SCI 0 Data Register Low; 0x000000CF */
volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2);     /* SCI 1 Control Register 1; 0x000000D2 */
volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3);     /* SCI 1 Control Register 2; 0x000000D3 */
volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4);     /* SCI 1 Status Register 1; 0x000000D4 */
volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5);     /* SCI 1 Status Register 2; 0x000000D5 */
volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6);     /* SCI 1 Data Register High; 0x000000D6 */
volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7);     /* SCI 1 Data Register Low; 0x000000D7 */
volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8);       /* SPI 0 Control Register; 0x000000D8 */
volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9);       /* SPI 0 Control Register 2; 0x000000D9 */
volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA);         /* SPI 0 Baud Rate Register; 0x000000DA */
volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB);         /* SPI 0 Status Register; 0x000000DB */
volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD);         /* SPI 0 Data Register; 0x000000DD */
volatile PWMESTR _PWME @(REG_BASE + 0x000000E0);           /* PWM Enable Register; 0x000000E0 */
volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1);       /* PWM Polarity Register; 0x000000E1 */
volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2);       /* PWM Clock Select Register; 0x000000E2 */
volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3);   /* PWM Prescale Clock Select Register; 0x000000E3 */
volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4);       /* PWM Center Align Enable Register; 0x000000E4 */
volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5);       /* PWM Control Register; 0x000000E5 */
volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8);     /* PWM Scale A Register; 0x000000E8 */
volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9);     /* PWM Scale B Register; 0x000000E9 */
volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE);       /* PWM Shutdown Register; 0x000000FE */
volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);     /* Flash Clock Divider Register; 0x00000100 */
volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);           /* Flash Security Register; 0x00000101 */
volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);         /* Flash Configuration Register; 0x00000103 */
volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);         /* Flash Protection Register; 0x00000104 */
volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);         /* Flash Status Register; 0x00000105 */
volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);           /* Flash Command Buffer and Register; 0x00000106 */
volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110);     /* EEPROM Clock Divider Register; 0x00000110 */
volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113);         /* EEPROM Configuration Register; 0x00000113 */
volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114);         /* EEPROM Protection Register; 0x00000114 */
volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115);         /* EEPROM Status Register; 0x00000115 */
volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116);           /* EEPROM Command Buffer and Register; 0x00000116 */
volatile LCDCR0STR _LCDCR0 @(REG_BASE + 0x00000120);       /* LCD Control Register 0; 0x00000120 */
volatile LCDCR1STR _LCDCR1 @(REG_BASE + 0x00000121);       /* LCD Control Register 1; 0x00000121 */
volatile FPENR0STR _FPENR0 @(REG_BASE + 0x00000122);       /* LCD Frontplane Enable Register 0; 0x00000122 */
volatile FPENR1STR _FPENR1 @(REG_BASE + 0x00000123);       /* LCD Frontplane Enable Register 1; 0x00000123 */
volatile FPENR2STR _FPENR2 @(REG_BASE + 0x00000124);       /* LCD Frontplane Enable Register 2; 0x00000124 */
volatile FPENR3STR _FPENR3 @(REG_BASE + 0x00000125);       /* LCD Frontplane Enable Register 3; 0x00000125 */
volatile LCDRAM0STR _LCDRAM0 @(REG_BASE + 0x00000128);     /* LCD RAM Register 0; 0x00000128 */
volatile LCDRAM1STR _LCDRAM1 @(REG_BASE + 0x00000129);     /* LCD RAM Register 1; 0x00000129 */
volatile LCDRAM2STR _LCDRAM2 @(REG_BASE + 0x0000012A);     /* LCD RAM Register 2; 0x0000012A */