memsetup.s

ARMboot is a firmware monitor/bootloader for embedded systems based on ARM or StrongARM CPUs

        str     r4,  [r1, #MDREFR_OFFSET]
        ldr     r4,  [r1, #MDREFR_OFFSET]

        @ deassert SLFRSH
        @
        bic     r4,  r4,  #0x00400000
        
        @ write back mdrefr
        @
        str     r4,  [r1, #MDREFR_OFFSET]

        @ assert E1PIN
        @
        orr     r4,  r4,  #0x00008000
        
        @ write back mdrefr
        @
        str     r4,  [r1, #MDREFR_OFFSET]
        ldr     r4,  [r1, #MDREFR_OFFSET]
        nop
        nop


@****************************************************************************
@  Step 4
@

        @ fetch platform value of mdcnfg
        @
        ldr     r2,  =CFG_MDCNFG_VAL                       

        @ disable all sdram banks
        @
        bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
        bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)

        @ program banks 0/1 for bus width
        @
        bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit


        @ write initial value of mdcnfg, w/o enabling sdram banks
        @
        str     r2,  [r1, #MDCNFG_OFFSET]

@ ****************************************************************************
@  Step 5
@
        
        @ pause for 200 uSecs
        @
    	ldr r3, =OSCR   @reset the OS Timer Count to zero
    	mov r2, #0 
	    str r2, [r3] 
	    ldr r4, =0x300			@really 0x2E1 is about 200usec, so 0x300 should be plenty
1:	
	    ldr r2, [r3] 
	    cmp r4, r2
	    bgt 1b
        

@****************************************************************************
@  Step 6
@

	    mov    r0, #0x78				    @turn everything off 
      mcr    p15, 0, r0, c1, c0, 0		@(caches off, MMU off, etc.)


@ ****************************************************************************
@  Step 7
@
        @ Access memory *not yet enabled* for CBR refresh cycles (8)
        @ - CBR is generated for all banks
        
	    ldr     r2, =CFG_DRAM_BASE
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]


@ ****************************************************************************
@  Step 8: NOP (enable dcache if you wanna... we dont)
@


@ ****************************************************************************
@  Step 9
@


        @get memory controller base address
        @
        ldr     r1,  =MEMC_BASE

        @fetch current mdcnfg value
        @
        ldr     r3,  [r1, #MDCNFG_OFFSET]

        @enable sdram bank 0 if installed (must do for any populated bank)
        @
        orr     r3,  r3,  #MDCNFG_DE0

        @write back mdcnfg, enabling the sdram bank(s)
        @
        str     r3,  [r1, #MDCNFG_OFFSET]


@****************************************************************************
@  Step 10
@
        
        @ write mdmrs
        @
        ldr     r2,  =CFG_MDMRS_VAL
        str     r2,  [r1, #MDMRS_OFFSET]
        
        
@****************************************************************************
@  Step 11: Final Step
@

@INITINTC        
        @********************************************************************
        @ Disable (mask) all interrupts at the interrupt controller
        @

        @ clear the interrupt level register (use IRQ, not FIQ)
        @
        mov     r1, #0
        ldr     r2,  =ICLR
        str     r1,  [r2]
        
        @ mask all interrupts at the controller
        @       
        ldr     r2,  =ICMR
        str     r1,  [r2]


@INITCLKS        
        @ ********************************************************************        
        @ Disable the peripheral clocks, and set the core clock
        @ frequency (hard-coding at 398.12MHz for now).
        @

		@ Turn Off ALL on-chip peripheral clocks for re-configuration
		@ *Note: See label 'ENABLECLKS' for the re-enabling
		@
        ldr     r1,  =CKEN
        mov     r2,  #0
        str     r2,  [r1]


        @ default value in case no valid rotary switch setting is found
        ldr     r2, =(CCCR_L27 | CCCR_M2 | CCCR_N10)        @ DEFAULT: {200/200/100}

           
        @... and write the core clock config register
        @
        ldr     r1,  =CCCR
        str     r2,  [r1]

/*        @ enable the 32Khz oscillator for RTC and PowerManager
        @
        ldr     r1,  =OSCC
        mov     r2,  #OSCC_OON  
        str     r2,  [r1]

	
        @ NOTE:  spin here until OSCC.OOK get set,
        @        meaning the PLL has settled.
        @ 
60:        
        ldr     r2, [r1]
        ands    r2, r2, #1
        beq     60b
*/

@OSCC_OON_DONE        


#ifdef  A0_COTULLA    
    @****************************************************************************
    @ !!! Take care of A0 Errata Sighting #4 -- 
    @ after a frequency change, the memory controller must be restarted
    @

        @ get memory controller base address
        ldr     r1,  =MEMC_BASE

        @ get the current state of MDREFR
        @
        ldr     r2,  [r1, #MDREFR_OFFSET]

        @ clear E0PIN, E1PIN
        @
        bic     r3,  r2,  #(MDREFR_E0PIN | MDREFR_E1PIN)

        @ write MDREFR with E0PIN, E1PIN cleared (disable sdclk[0,1])
        @
        str     r3,  [r1, #MDREFR_OFFSET]

        @ then write MDREFR with E0PIN, E1PIN set (enable sdclk[0,1])
        @
        str     r2,  [r1, #MDREFR_OFFSET]

        @ get the current state of MDCNFG
        @
        ldr     r3,  [r1, #MDCNFG_OFFSET]

        @ disable all SDRAM banks
        @
        bic     r3,  r3,  #(MDCNFG_DE0 | MDCNFG_DE1)
        bic     r3,  r3,  #(MDCNFG_DE2 |  MDCNFG_DE3)
     
        @ write back MDCNFG   
        @
        ldr     r3,  [r1, #MDCNFG_OFFSET]

	    @ Access memory not yet enabled for CBR refresh cycles (8)
        @ - CBR is generated for *all* banks
	    ldr     r2, =CFG_DRAM_BASE
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]

        @ fetch current mdcnfg value
        @
        ldr     r3,  [r1, #MDCNFG_OFFSET]

        @ enable sdram bank 0 if installed
        @
        orr     r3,  r3,  #MDCNFG_DE0

        @ write back mdcnfg, enabling the sdram bank(s)
        @
        str     r3,  [r1, #MDCNFG_OFFSET]

        @ write mdmrs
        @
        ldr     r2,  =CFG_MDMRS_VAL
        str     r2,  [r1, #MDMRS_OFFSET]

        
        
    //    @ errata: don't enable auto power-down
        @ get current value of mdrefr
        @ldr     r3,  [r1, #MDREFR_OFFSET]
        @ enable auto-power down 
        @orr     r3,  r3,  #MDREFR_APD
        @write back mdrefr
        @str     r3,  [r1, #MDREFR_OFFSET]
    
#endif A0_Cotulla


  ldr     r0, =0x000C0dE3
  ldr    	r1, =_LED
  str    	r0, [r1]    		// hex display

@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
@ ^%^%^%^%^%^%^%^%^%   above could be replaced by prememLLI ^%^%^%^%^%^%^%^%^%
@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%


	// Save SDRAM size
    ldr     r1, =DRAM_SIZE  
	 str	   r8, [r1]
   
    ldr     r0, =0xC0DE0006
    ldr    	r1, =_LED
    str    	r0, [r1]    		// hex display
  
	// Interrupt init
	// Mask all interrupts
    ldr	r0, =ICMR // enable no sources
	mov r1, #0
    str r1, [r0]

#define NODEBUG
#ifdef NODEBUG
	//Disable software and data breakpoints
	mov	r0,#0
	mcr	p15,0,r0,c14,c8,0  // ibcr0
	mcr	p15,0,r0,c14,c9,0  // ibcr1
	mcr	p15,0,r0,c14,c4,0  // dbcon

	//Enable all debug functionality
	mov	r0,#0x80000000
	mcr	p14,0,r0,c10,c0,0  // dcsr

#endif

	ldr     r0, =0xBEEF001D
    ldr    	r1, =_LED
    str    	r0, [r1]    		// hex display
  
	mov	pc, r10

@ End memsetup
  
@ %%%%%%%%%%%   Useful subroutines
GET_S23:
    @ This macro will read S23 and return its value in r3
    @ r2 contains the base address of the Lubbock user registers
    ldr r2, =FPGA_REGS_BASE_PHYSICAL

    //@ read S23's value        
    ldr     r3, [r2, #USER_SWITCHES_OFFSET]
    
    @ mask out irrelevant bits
    and     r3, r3, #0x200
    
    @ get bit into position 0
    mov     r3, r3, LSR #9

    mov     pc, lr
@ End GET_S23


GET_S24:
    @ This macro will read S24 and return its value in r0
    @ r2 contains the base address of the Lubbock user registers
    ldr r2, =FPGA_REGS_BASE_PHYSICAL

    //@ read S24's value        
    ldr     r0, [r2, #USER_SWITCHES_OFFSET]
    
    @ mask out irrelevant bits
    and     r0, r0, #0x100
    
    @ get bit into position 0
    mov     r0, r0, LSR #8

    mov     pc, lr
@ End GET_S23


GET_S25:
    @ This macro will read rotary S25 and return its value in r0
    @ r2 contains the base address of the Lubbock user registers
    @ read the user switches register      
    ldr     r0, [r2, #USER_SWITCHES_OFFSET]
    
    @ mask out irrelevant bits
    and     r0, r0, #0xF0

    mov     pc, lr
@ End subroutine


GET_S26:
    @ This macro will read rotary S26 and return its value in r3
    @ r2 contains the base address of the Lubbock user registers
    @ read the user switches register       
    ldr     r3, [r2, #USER_SWITCHES_OFFSET]
        
    @ mask out irrelevant bits
    and     r3, r3, #0x0F

    mov     pc, lr
@ End subroutine GET_S26