📄 c5402mmr.h
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/*=============================================================================*/
/*All software and related documentation is provided "AS IS" and without */
/*warranty or support of any kind and Texas Instruments expressly disclaims */
/*all other warranties,express or implied, including, but not limited to, the */
/*implied warranties of merchantability and fitness for a particular purpose. */
/*Under no circumstances shall Texas Instruments be liable for any incidental, */
/*special or consequential damages that result from the use or inability to */
/*use the software or related documentation, even if Texas Instruments has */
/*been advised of the liability. */
/* */
/*Unless otherwise stated, software written and copyrighted by Texas */
/*Instruments is distributed as "freeware". You may use and modify this */
/*software without any charge or restriction. You may distribute to others, */
/*as long as the original author is acknowledged. */
/*=============================================================================*/
/******************************************************************/
/* Define Interrupt Flag and Interrupt Mask Registers */
/******************************************************************/
#define IMR_BASE 0x00
#define IMR_ADDR ((volatile IMR_REG *) ((char *) IMR_BASE))
#define IFR_BASE 0x01
#define IFR_ADDR ((volatile IFR_REG *) ((char *) IFR_BASE))
typedef union {
struct {
unsigned int res :2;
unsigned int dmac5 :1;
unsigned int dmac4 :1;
unsigned int bxint1 :1;
unsigned int brint1 :1;
unsigned int hint :1;
unsigned int int3 :1;
unsigned int dmac1 :1;
unsigned int dmac0 :1;
unsigned int bxint0 :1;
unsigned int brint0 :1;
unsigned int tint0 :1;
unsigned int int2 :1;
unsigned int int1 :1;
unsigned int int0 :1;
} bitval;
unsigned int value;
} IFR_REG;
typedef union {
struct {
unsigned int res :2;
unsigned int dmac5 :1;
unsigned int dmac4 :1;
unsigned int bxint1 :1;
unsigned int brint1 :1;
unsigned int hint :1;
unsigned int int3 :1;
unsigned int dmac1 :1;
unsigned int dmac0 :1;
unsigned int bxint0 :1;
unsigned int brint0 :1;
unsigned int tint0 :1;
unsigned int int2 :1;
unsigned int int1 :1;
unsigned int int0 :1;
} bitval;
unsigned int value;
} IMR_REG;
/******************************************************************/
/*Status Registers */
/******************************************************************/
#define ST0_BASE 0x06
#define ST1_BASE 0x07
#define ST0_ADDR ((volatile ST0_REG *) ((char *) ST0_BASE))
#define ST1_ADDR ((volatile ST1_REG *) ((char *) ST1_BASE))
typedef union {
struct {
unsigned int arp :3;
unsigned int tc :1;
unsigned int c :1;
unsigned int ova :1;
unsigned int ovb :1;
unsigned int dp :9;
} bitval;
unsigned int value;
} ST0_REG;
typedef union {
struct {
unsigned int braf :1;
unsigned int cpl :1;
unsigned int xf :1;
unsigned int hm :1;
unsigned int intm :1;
unsigned int zero :1;
unsigned int ovm :1;
unsigned int sxm :1;
unsigned int c16 :1;
unsigned int frct :1;
unsigned int cmpt :1;
unsigned int asmm :5;
} bitval;
unsigned int value;
} ST1_REG;
/******************************************************************/
/*Accumulators */
/******************************************************************/
#define AL_BASE 0x08
#define AH_BASE 0x09
#define AG_BASE 0x0A
#define BL_BASE 0x0B
#define BH_BASE 0x0C
#define BG_BASE 0x0D
#define AL_REG (*(volatile unsigned int *)AL_BASE) /* ACCUMULATOR A Low Word */
#define AH_REG (*(volatile unsigned int *)AH_BASE) /* ACCUMULATOR A High Word */
#define AG_REG (*(volatile unsigned int *)AG_BASE) /* ACCUMULATOR A Guard Bits */
#define BL_REG (*(volatile unsigned int *)BL_BASE) /* ACCUMULATOR B Low Word */
#define BH_REG (*(volatile unsigned int *)BH_BASE) /* ACCUMULATOR B High Word */
#define BG_REG (*(volatile unsigned int *)BG_BASE) /* ACCUMULATOR B Guard Bits */
/******************************************************************/
/* Registers */
/******************************************************************/
#define TREG_BASE 0x0E
#define TRN_BASE 0x0F
#define AR0_BASE 0x10
#define AR1_BASE 0x11
#define AR2_BASE 0x12
#define AR3_BASE 0x13
#define AR4_BASE 0x14
#define AR5_BASE 0x15
#define AR6_BASE 0x16
#define AR7_BASE 0x17
#define SP_BASE 0x18
#define BK_BASE 0x19
#define BRC_BASE 0x1A
#define RSA_BASE 0x1B
#define REA_BASE 0x1C
#define TREG_REG (*(volatile unsigned int *)TREG_BASE) /* Temporary Register */
#define TRN_REG (*(volatile unsigned int *)TRN_BASE) /* TRN_ransition Register */
#define AR0_REG (*(volatile unsigned int *)AR0_BASE) /* AR0_uxiliary Register 0 */
#define AR1_REG (*(volatile unsigned int *)AR1_BASE) /* Auxiliary Register 1 */
#define AR2_REG (*(volatile unsigned int *)AR2_BASE) /* Auxiliary Register 2 */
#define AR3_REG (*(volatile unsigned int *)AR3_BASE) /* Auxiliary Register 3 */
#define AR4_REG (*(volatile unsigned int *)AR4_BASE) /* Auxiliary Register 4 */
#define AR5_REG (*(volatile unsigned int *)AR5_BASE) /* Auxiliary Register 5 */
#define AR6_REG (*(volatile unsigned int *)AR6_BASE) /* Auxiliary Register 6 */
#define AR7_REG (*(volatile unsigned int *)AR7_BASE) /* Auxiliary Register 7 */
#define SP_REG (*(volatile unsigned int *)SP_BASE) /* Stack Pointer */
#define BK_REG (*(volatile unsigned int *)BK_BASE) /* Circular Buffer size register */
#define BRC_REG (*(volatile unsigned int *)BRC_BASE) /* Block Repeat Counter */
#define RSA_REG (*(volatile unsigned int *)RSA_BASE) /* Block Repeat Start Address */
#define REA_REG (*(volatile unsigned int *)REA_BASE) /* Block Repeat End Address */
/******************************************************************/
/*PMST */
/******************************************************************/
#define PMST_BASE 0x1d
#define PMST_ADDR ((volatile PMST_REG *) ((char *) PMST_BASE))
typedef union {
struct {
unsigned int iptr :9;
unsigned int mpmc :1;
unsigned int ovly :1;
unsigned int avis :1;
unsigned int drom :1;
unsigned int clkoff :1;
unsigned int smul :1;
unsigned int sst :1;
} bitval;
unsigned int value;
} PMST_REG;
/*********************************************************************/
/* Extended Program Counter -XPC register */
/*********************************************************************/
#define XPC_BASE 0x1e
#define XPC_ADDR *(volatile unsigned int *)XPC_BASE
/*********************************************************************/
/* EXTERNAL BUS CONTROL REGISTERS */
/*********************************************************************/
#define SWWSR_BASE 0x28
#define SWWSR_ADDR ((volatile SWWSR_REG *) ((char *) SWWSR_BASE))
#define BSCR_BASE 0x29
#define BSCR_ADDR ((volatile BSCR_REG *) ((char *) BSCR_BASE))
#define SWCR_BASE 0x2B
#define SWCR_ADDR ((volatile SWCR_REG *) ((char *) SWCR_BASE))
typedef union {
struct {
unsigned int xpa :1;
unsigned int io :3;
unsigned int data_hi :3;
unsigned int data_low :3;
unsigned int prog_hi :3;
unsigned int prog_low :3;
} bitval;
unsigned int value;
} SWWSR_REG;
typedef union {
struct {
unsigned int bnkcmp :4;
unsigned int psds :1;
unsigned int resvd :8;
unsigned int hbh :1;
unsigned int bh :1;
unsigned int exio :1;
} bitval;
unsigned int value;
} BSCR_REG;
typedef union {
struct {
unsigned int reserved :15;
unsigned int swsm :1;
} bitval;
unsigned int value;
} SWCR_REG;
/*********************************************************************/
/* HOST PORT INTERFACE REGISTER ADDRESS */
/*********************************************************************/
#define HPIC_BASE 0x2c
#define HPIC_ADDR ((volatile HPIC_REG *) ((char *) HPIC_BASE))
typedef union {
struct {
unsigned int zero3 :3;
unsigned int xhpia2 :1;
unsigned int hint2 :1;
unsigned int dspint2 :1;
unsigned int zero2 :1;
unsigned int bob2 :1;
unsigned int hpiena :1;
unsigned int rsvd :2;
unsigned int xhpia :1;
unsigned int hint :1;
unsigned int dspint :1;
unsigned int zero :1;
unsigned int bob :1;
} bitval;
unsigned int value;
} HPIC_REG;
/*********************************************************************/
/* Structure for McBSP */
/*********************************************************************/
/*-------------------------------------------------------------------*/
/* McBSP 0 */
/*-------------------------------------------------------------------*/
#define DRR20_BASE 0x20
#define DRR10_BASE 0x21
#define DXR20_BASE 0x22
#define DXR10_BASE 0x23
#define SPSA0_BASE 0x38
#define SPCR10_BASE 0x39
#define SPCR20_BASE 0x39
#define RCR10_BASE 0x39
#define RCR20_BASE 0x39
#define XCR10_BASE 0x39
#define XCR20_BASE 0x39
#define SRGR10_BASE 0x39
#define SRGR20_BASE 0x39
#define MCR10_BASE 0x39
#define MCR20_BASE 0x39
#define RCERA0_BASE 0x39
#define RCERB0_BASE 0x39
#define XCERA0_BASE 0x39
#define XCERB0_BASE 0x39
#define PCR0_BASE 0x39
#define SPCR10_SUB 0x00
#define SPCR20_SUB 0x01
#define RCR10_SUB 0x02
#define RCR20_SUB 0x03
#define XCR10_SUB 0x04
#define XCR20_SUB 0x05
#define SRGR10_SUB 0x06
#define SRGR20_SUB 0x07
#define MCR10_SUB 0x08
#define MCR20_SUB 0x09
#define RCERA0_SUB 0x0A
#define RCERB0_SUB 0x0B
#define XCERA0_SUB 0x0C
#define XCERB0_SUB 0x0D
#define PCR0_SUB 0x0E
#define DRR20_ADDR (*(volatile unsigned int *)DRR20_BASE)
#define DRR10_ADDR (*(volatile unsigned int *)DRR10_BASE)
#define DXR20_ADDR (*(volatile unsigned int *)DXR20_BASE)
#define DXR10_ADDR (*(volatile unsigned int *)DXR10_BASE)
#define SPSA0_ADDR (*(volatile unsigned int *)SPSA0_BASE)
#define SPCR10_ADDR ((volatile SPCR1_REG *) ((char *) SPCR10_BASE))
#define SPCR20_ADDR ((volatile SPCR2_REG *) ((char *) SPCR20_BASE))
#define RCR10_ADDR ((volatile RCR1_REG *) ((char *) RCR10_BASE))
#define RCR20_ADDR ((volatile RCR2_REG *) ((char *) RCR20_BASE))
#define XCR10_ADDR ((volatile XCR1_REG *) ((char *) XCR10_BASE))
#define XCR20_ADDR ((volatile XCR2_REG *) ((char *) XCR20_BASE))
#define SRGR10_ADDR ((volatile SRGR1_REG *) ((char *) SRGR10_BASE))
#define SRGR20_ADDR ((volatile SRGR2_REG *) ((char *) SRGR20_BASE))
#define MCR10_ADDR ((volatile MCR1_REG *) ((char *) MCR10_BASE))
#define MCR20_ADDR ((volatile MCR2_REG *) ((char *) MCR20_BASE))
#define RCERA0_ADDR ((volatile RCERA_REG *) ((char *) RCERA0_BASE))
#define RCERB0_ADDR ((volatile RCERB_REG *) ((char *) RCERB0_BASE))
#define XCERA0_ADDR ((volatile XCERA_REG *) ((char *) XCERA0_BASE))
#define XCERB0_ADDR ((volatile XCERB_REG *) ((char *) XCERB0_BASE))
#define PCR0_ADDR ((volatile PCR_REG *) ((char *) PCR0_BASE))
/*-------------------------------------------------------------------*/
/* McBSP 1 */
/*-------------------------------------------------------------------*/
#define DRR21_BASE 0x40
#define DRR11_BASE 0x41
#define DXR21_BASE 0x42
#define DXR11_BASE 0x43
#define SPSA1_BASE 0x48
#define SPCR11_BASE 0x49
#define SPCR21_BASE 0x49
#define RCR11_BASE 0x49
#define RCR21_BASE 0x49
#define XCR11_BASE 0x49
#define XCR21_BASE 0x49
#define SRGR11_BASE 0x49
#define SRGR21_BASE 0x49
#define MCR11_BASE 0x49
#define MCR21_BASE 0x49
#define RCERA1_BASE 0x49
#define RCERB1_BASE 0x49
#define XCERA1_BASE 0x49
#define XCERB1_BASE 0x49
#define PCR1_BASE 0x49
#define SPCR11_SUB 0x00
#define SPCR21_SUB 0x01
#define RCR11_SUB 0x02
#define RCR21_SUB 0x03
#define XCR11_SUB 0x04
#define XCR21_SUB 0x05
#define SRGR11_SUB 0x06
#define SRGR21_SUB 0x07
#define MCR11_SUB 0x08
#define MCR21_SUB 0x09
#define RCERA1_SUB 0x0A
#define RCERB1_SUB 0x0B
#define XCERA1_SUB 0x0C
#define XCERB1_SUB 0x0D
#define PCR1_SUB 0x0E
#define DRR21_ADDR (*(volatile unsigned int *)DRR21_BASE)
#define DRR11_ADDR (*(volatile unsigned int *)DRR11_BASE)
#define DXR21_ADDR (*(volatile unsigned int *)DXR21_BASE)
#define DXR11_ADDR (*(volatile unsigned int *)DXR11_BASE)
#define SPSA1_ADDR (*(volatile unsigned int *)SPSA1_BASE)
#define SPCR11_ADDR ((volatile SPCR1_REG *) ((char *) SPCR11_BASE))
#define SPCR21_ADDR ((volatile SPCR2_REG *) ((char *) SPCR21_BASE))
#define RCR11_ADDR ((volatile RCR1_REG *) ((char *) RCR11_BASE))
#define RCR21_ADDR ((volatile RCR2_REG *) ((char *) RCR21_BASE))
#define XCR11_ADDR ((volatile XCR1_REG *) ((char *) XCR11_BASE))
#define XCR21_ADDR ((volatile XCR2_REG *) ((char *) XCR21_BASE))
#define SRGR11_ADDR ((volatile SRGR1_REG *) ((char *) SRGR11_BASE))
#define SRGR21_ADDR ((volatile SRGR2_REG *) ((char *) SRGR21_BASE))
#define MCR11_ADDR ((volatile MCR1_REG *) ((char *) MCR11_BASE))
#define MCR21_ADDR ((volatile MCR2_REG *) ((char *) MCR21_BASE))
#define RCERA1_ADDR ((volatile RCERA_REG *) ((char *) RCERA1_BASE))
#define RCERB1_ADDR ((volatile RCERB_REG *) ((char *) RCERB1_BASE))
#define XCERA1_ADDR ((volatile XCERA_REG *) ((char *) XCERA1_BASE))
#define XCERB1_ADDR ((volatile XCERB_REG *) ((char *) XCERB1_BASE))
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