step_a.hier_info

来自「步进的控制电机控制 c++环境下开发」· HIER_INFO 代码 · 共 1,621 行 · 第 1/4 页

address_b[3] => ram_block3a10.PORTBADDR3
address_b[3] => ram_block3a11.PORTBADDR3
address_b[3] => ram_block3a12.PORTBADDR3
address_b[3] => ram_block3a13.PORTBADDR3
address_b[3] => ram_block3a14.PORTBADDR3
address_b[3] => ram_block3a15.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[4] => ram_block3a8.PORTBADDR4
address_b[4] => ram_block3a9.PORTBADDR4
address_b[4] => ram_block3a10.PORTBADDR4
address_b[4] => ram_block3a11.PORTBADDR4
address_b[4] => ram_block3a12.PORTBADDR4
address_b[4] => ram_block3a13.PORTBADDR4
address_b[4] => ram_block3a14.PORTBADDR4
address_b[4] => ram_block3a15.PORTBADDR4
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock0 => ram_block3a8.CLK0
clock0 => ram_block3a9.CLK0
clock0 => ram_block3a10.CLK0
clock0 => ram_block3a11.CLK0
clock0 => ram_block3a12.CLK0
clock0 => ram_block3a13.CLK0
clock0 => ram_block3a14.CLK0
clock0 => ram_block3a15.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1
clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
clock1 => ram_block3a8.CLK1
clock1 => ram_block3a9.CLK1
clock1 => ram_block3a10.CLK1
clock1 => ram_block3a11.CLK1
clock1 => ram_block3a12.CLK1
clock1 => ram_block3a13.CLK1
clock1 => ram_block3a14.CLK1
clock1 => ram_block3a15.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
data_b[4] => ram_block3a4.PORTBDATAIN
data_b[5] => ram_block3a5.PORTBDATAIN
data_b[6] => ram_block3a6.PORTBDATAIN
data_b[7] => ram_block3a7.PORTBDATAIN
data_b[8] => ram_block3a8.PORTBDATAIN
data_b[9] => ram_block3a9.PORTBDATAIN
data_b[10] => ram_block3a10.PORTBDATAIN
data_b[11] => ram_block3a11.PORTBDATAIN
data_b[12] => ram_block3a12.PORTBDATAIN
data_b[13] => ram_block3a13.PORTBDATAIN
data_b[14] => ram_block3a14.PORTBDATAIN
data_b[15] => ram_block3a15.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_a[4] <= ram_block3a4.PORTADATAOUT
q_a[5] <= ram_block3a5.PORTADATAOUT
q_a[6] <= ram_block3a6.PORTADATAOUT
q_a[7] <= ram_block3a7.PORTADATAOUT
q_a[8] <= ram_block3a8.PORTADATAOUT
q_a[9] <= ram_block3a9.PORTADATAOUT
q_a[10] <= ram_block3a10.PORTADATAOUT
q_a[11] <= ram_block3a11.PORTADATAOUT
q_a[12] <= ram_block3a12.PORTADATAOUT
q_a[13] <= ram_block3a13.PORTADATAOUT
q_a[14] <= ram_block3a14.PORTADATAOUT
q_a[15] <= ram_block3a15.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
q_b[8] <= ram_block3a8.PORTBDATAOUT
q_b[9] <= ram_block3a9.PORTBDATAOUT
q_b[10] <= ram_block3a10.PORTBDATAOUT
q_b[11] <= ram_block3a11.PORTBDATAOUT
q_b[12] <= ram_block3a12.PORTBDATAOUT
q_b[13] <= ram_block3a13.PORTBDATAOUT
q_b[14] <= ram_block3a14.PORTBDATAOUT
q_b[15] <= ram_block3a15.PORTBDATAOUT
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE
wren_b => ram_block3a4.PORTBRE
wren_b => ram_block3a5.PORTBRE
wren_b => ram_block3a6.PORTBRE
wren_b => ram_block3a7.PORTBRE
wren_b => ram_block3a8.PORTBRE
wren_b => ram_block3a9.PORTBRE
wren_b => ram_block3a10.PORTBRE
wren_b => ram_block3a11.PORTBRE
wren_b => ram_block3a12.PORTBRE
wren_b => ram_block3a13.PORTBRE
wren_b => ram_block3a14.PORTBRE
wren_b => ram_block3a15.PORTBRE


|step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= ram_rom_incr_addr~1.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
data_write[8] <= ram_rom_data_reg[8].DB_MAX_OUTPUT_PORT_TYPE
data_write[9] <= ram_rom_data_reg[9].DB_MAX_OUTPUT_PORT_TYPE
data_write[10] <= ram_rom_data_reg[10].DB_MAX_OUTPUT_PORT_TYPE
data_write[11] <= ram_rom_data_reg[11].DB_MAX_OUTPUT_PORT_TYPE
data_write[12] <= ram_rom_data_reg[12].DB_MAX_OUTPUT_PORT_TYPE
data_write[13] <= ram_rom_data_reg[13].DB_MAX_OUTPUT_PORT_TYPE
data_write[14] <= ram_rom_data_reg[14].DB_MAX_OUTPUT_PORT_TYPE
data_write[15] <= ram_rom_data_reg[15].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~31.DATAB
data_read[1] => ram_rom_data_reg~30.DATAB
data_read[2] => ram_rom_data_reg~29.DATAB
data_read[3] => ram_rom_data_reg~28.DATAB
data_read[4] => ram_rom_data_reg~27.DATAB
data_read[5] => ram_rom_data_reg~26.DATAB
data_read[6] => ram_rom_data_reg~25.DATAB
data_read[7] => ram_rom_data_reg~24.DATAB
data_read[8] => ram_rom_data_reg~23.DATAB
data_read[9] => ram_rom_data_reg~22.DATAB
data_read[10] => ram_rom_data_reg~21.DATAB
data_read[11] => ram_rom_data_reg~20.DATAB
data_read[12] => ram_rom_data_reg~19.DATAB
data_read[13] => ram_rom_data_reg~18.DATAB
data_read[14] => ram_rom_data_reg~17.DATAB
data_read[15] => ram_rom_data_reg~16.DATAB
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_data_reg[15].CLK
raw_tck => ram_rom_data_reg[14].CLK
raw_tck => ram_rom_data_reg[13].CLK
raw_tck => ram_rom_data_reg[12].CLK
raw_tck => ram_rom_data_reg[11].CLK
raw_tck => ram_rom_data_reg[10].CLK
raw_tck => ram_rom_data_reg[9].CLK
raw_tck => ram_rom_data_reg[8].CLK
raw_tck => ram_rom_data_reg[7].CLK
raw_tck => ram_rom_data_reg[6].CLK
raw_tck => ram_rom_data_reg[5].CLK
raw_tck => ram_rom_data_reg[4].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[4].CLK
raw_tck => ram_rom_data_shift_cntr_reg[3].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ram_rom_incr_write_addr_reg.CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => bypass_reg_out.CLK
raw_tck => is_in_use_reg.CLK
raw_tck => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TCK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => tck_usr.DATAIN
tdi => ram_rom_addr_reg~0.DATAB
tdi => ram_rom_data_reg~0.DATAB
tdi => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TDI
tdi => bypass_reg_out.DATAIN
usr1 => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.USR1
usr1 => dr_scan.IN0
usr1 => name_gen~0.IN0
jtag_state_cdr => name_gen~1.IN1
jtag_state_sdr => sdr.IN0
jtag_state_sdr => name_gen~1.IN0
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.SHIFT
jtag_state_e1dr => e1dr.IN1
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.UPDATE
jtag_state_uir => ~NO_FANOUT~
clrn => bypass_reg_out.ACLR
clrn => is_in_use_reg.ACLR
ena => dr_scan.IN1
ena => name_gen~0.IN1
ena => bypass_reg_out.ENA
ir_in[0] => ram_rom_addr_reg[3].ACLR
ir_in[0] => ram_rom_addr_reg[2].ACLR
ir_in[0] => ram_rom_addr_reg[1].ACLR
ir_in[0] => ram_rom_addr_reg[0].ACLR
ir_in[0] => ir_loaded_address_reg[3].ACLR
ir_in[0] => ir_loaded_address_reg[2].ACLR
ir_in[0] => ir_loaded_address_reg[1].ACLR
ir_in[0] => ir_loaded_address_reg[0].ACLR
ir_in[0] => tdo~1.OUTPUTSELECT
ir_in[0] => is_in_use_reg~1.OUTPUTSELECT
ir_in[0] => ram_rom_addr_reg[4].ACLR
ir_in[1] => process1~0.IN1
ir_in[1] => process1~2.IN0
ir_in[1] => ram_rom_incr_addr~0.IN0
ir_in[2] => process1~0.IN0
ir_in[2] => ram_rom_incr_addr~1.IN1
ir_in[3] => process0~0.IN1
ir_in[3] => process1~3.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[3].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR
ir_in[3] => process5~0.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[4].ACLR
ir_in[4] => is_in_use_reg~0.OUTPUTSELECT
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE
irq <= <GND>
tdo <= tdo~1.DB_MAX_OUTPUT_PORT_TYPE


|step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
ROM_DATA[0] => Mux~0.IN134
ROM_DATA[0] => Mux~1.IN134
ROM_DATA[0] => Mux~2.IN134
ROM_DATA[0] => Mux~3.IN134
ROM_DATA[1] => Mux~0.IN133
ROM_DATA[1] => Mux~1.IN133
ROM_DATA[1] => Mux~2.IN133
ROM_DATA[1] => Mux~3.IN133
ROM_DATA[2] => Mux~0.IN132
ROM_DATA[2] => Mux~1.IN132
ROM_DATA[2] => Mux~2.IN132
ROM_DATA[2] => Mux~3.IN132
ROM_DATA[3] => Mux~0.IN131
ROM_DATA[3] => Mux~1.IN131
ROM_DATA[3] => Mux~2.IN131
ROM_DATA[3] => Mux~3.IN131
ROM_DATA[4] => Mux~0.IN130
ROM_DATA[4] => Mux~1.IN130
ROM_DATA[4] => Mux~2.IN130
ROM_DATA[4] => Mux~3.IN130
ROM_DATA[5] => Mux~0.IN129
ROM_DATA[5] => Mux~1.IN129
ROM_DATA[5] => Mux~2.IN129
ROM_DATA[5] => Mux~3.IN129
ROM_DATA[6] => Mux~0.IN128
ROM_DATA[6] => Mux~1.IN128
ROM_DATA[6] => Mux~2.IN128
ROM_DATA[6] => Mux~3.IN128
ROM_DATA[7] => Mux~0.IN127
ROM_DATA[7] => Mux~1.IN127
ROM_DATA[7] => Mux~2.IN127
ROM_DATA[7] => Mux~3.IN127
ROM_DATA[8] => Mux~0.IN126
ROM_DATA[8] => Mux~1.IN126
ROM_DATA[8] => Mux~2.IN126
ROM_DATA[8] => Mux~3.IN126
ROM_DATA[9] => Mux~0.IN125
ROM_DATA[9] => Mux~1.IN125
ROM_DATA[9] => Mux~2.IN125
ROM_DATA[9] => Mux~3.IN125
ROM_DATA[10] => Mux~0.IN124
ROM_DATA[10] => Mux~1.IN124
ROM_DATA[10] => Mux~2.IN124
ROM_DATA[10] => Mux~3.IN124
ROM_DATA[11] => Mux~0.IN123
ROM_DATA[11] => Mux~1.IN123
ROM_DATA[11] => Mux~2.IN123
ROM_DATA[11] => Mux~3.IN123
ROM_DATA[12] => Mux~0.IN122
ROM_DATA[12] => Mux~1.IN122
ROM_DATA[12] => Mux~2.IN122
ROM_DATA[12] => Mux~3.IN122
ROM_DATA[13] => Mux~0.IN121
ROM_DATA[13] => Mux~1.IN121
ROM_DATA[13] => Mux~2.IN121
ROM_DATA[13] => Mux~3.IN121
ROM_DATA[14] => Mux~0.IN120
ROM_DATA[14] => Mux~1.IN120
ROM_DATA[14] => Mux~2.IN120
ROM_DATA[14] => Mux~3.IN120
ROM_DATA[15] => Mux~0.IN119
ROM_DATA[15] => Mux~1.IN119
ROM_DATA[15] => Mux~2.IN119
ROM_DATA[15] => Mux~3.IN119
ROM_DATA[16] => Mux~0.IN118
ROM_DATA[16] => Mux~1.IN118
ROM_DATA[16] => Mux~2.IN118
ROM_DATA[16] => Mux~3.IN118
ROM_DATA[17] => Mux~0.IN117
ROM_DATA[17] => Mux~1.IN117
ROM_DATA[17] => Mux~2.IN117
ROM_DATA[17] => Mux~3.IN117
ROM_DATA[18] => Mux~0.IN116
ROM_DATA[18] => Mux~1.IN116
ROM_DATA[18] => Mux~2.IN116
ROM_DATA[18] => Mux~3.IN116
ROM_DATA[19] => Mux~0.IN115
ROM_DATA[19] => Mux~1.IN115
ROM_DATA[19] => Mux~2.IN115
ROM_DATA[19] => Mux~3.IN115
ROM_DATA[20] => Mux~0.IN114
ROM_DATA[20] => Mux~1.IN114
ROM_DATA[20] => Mux~2.IN114
ROM_DATA[20] => Mux~3.IN114
ROM_DATA[21] => Mux~0.IN113
ROM_DATA[21] => Mux~1.IN113
ROM_DATA[21] => Mux~2.IN113
ROM_DATA[21] => Mux~3.IN113
ROM_DATA[22] => Mux~0.IN112
ROM_DATA[22] => Mux~1.IN112
ROM_DATA[22] => Mux~2.IN112
ROM_DATA[22] => Mux~3.IN112
ROM_DATA[23] => Mux~0.IN111
ROM_DATA[23] => Mux~1.IN111
ROM_DATA[23] => Mux~2.IN111
ROM_DATA[23] => Mux~3.IN111
ROM_DATA[24] => Mux~0.IN110
ROM_DATA[24] => Mux~1.IN110
ROM_DATA[24] => Mux~2.IN110
ROM_DATA[24] => Mux~3.IN110
ROM_DATA[25] => Mux~0.IN109
ROM_DATA[25] => Mux~1.IN109
ROM_DATA[25] => Mux~2.IN109
ROM_DATA[25] => Mux~3.IN109
ROM_DATA[26] => Mux~0.IN108
ROM_DATA[26] => Mux~1.IN108
ROM_DATA[26] => Mux~2.IN108
ROM_DATA[26] => Mux~3.IN108
ROM_DATA[27] => Mux~0.IN107
ROM_DATA[27] => Mux~1.IN107
ROM_DATA[27] => Mux~2.IN107
ROM_DATA[27] => Mux~3.IN107
ROM_DATA[28] => Mux~0.IN106
ROM_DATA[28] => Mux~1.IN106
ROM_DATA[28] => Mux~2.IN106
ROM_DATA[28] => Mux~3.IN106
ROM_DATA[29] => Mux~0.IN105
ROM_DATA[29] => Mux~1.IN105
ROM_DATA[29] => Mux~2.IN105
ROM_DATA[29] => Mux~3.IN105
ROM_DATA[30] => Mux~0.IN104
ROM_DATA[30] => Mux~1.IN104
ROM_DATA[30] => Mux~2.IN104
ROM_DATA[30] => Mux~3.IN104
ROM_DATA[31] => Mux~0.IN103
ROM_DATA[31] => Mux~1.IN103
ROM_DATA[31] => Mux~2.IN103
ROM_DATA[31] => Mux~3.IN103
ROM_DATA[32] => Mux~0.IN102
ROM_DATA[32] => Mux~1.IN102
ROM_DATA[32] => Mux~2.IN102
ROM_DATA[32] => Mux~3.IN102
ROM_DATA[33] => Mux~0.IN101
ROM_DATA[33] => Mux~1.IN101
ROM_DATA[33] => Mux~2.IN101
ROM_DATA[33] => Mux~3.IN101
ROM_DATA[34] => Mux~0.IN100
ROM_DATA[34] => Mux~1.IN100
ROM_DATA[34] => Mux~2.IN100
ROM_DATA[34] => Mux~3.IN100
ROM_DATA[35] => Mux~0.IN99
ROM_DATA[35] => Mux~1.IN99
ROM_DATA[35] => Mux~2.IN99
ROM_DATA[35] => Mux~3.IN99
ROM_DATA[36] => Mux~0.IN98
ROM_DATA[36] => Mux~1.IN98
ROM_DATA[36] => Mux~2.IN98
ROM_DATA[36] => Mux~3.IN98
ROM_DATA[37] => Mux~0.IN97
ROM_DATA[37] => Mux~1.IN97
ROM_DATA[37] => Mux~2.IN97
ROM_DATA[37] => Mux~3.IN97
ROM_DATA[38] => Mux~0.IN96
ROM_DATA[38] => Mux~1.IN96
ROM_DATA[38] => Mux~2.IN96
ROM_DATA[38] => Mux~3.IN96
ROM_DATA[39] => Mux~0.IN95