step_a.tan.summary

来自「步进的控制电机控制 c++环境下开发」· SUMMARY 代码 · 共 137 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -0.347 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 25.186 ns
From           : rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg9
To             : Y[2]
From Clock     : clk0
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 13.730 ns
From           : S
To             : Y[2]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.795 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.314 ns
From           : FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[9]
To             : D[9]
From Clock     : F1HZ
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : 1.863 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 159.39 MHz ( period = 6.274 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]
To             : sld_hub:sld_hub_inst|HUB_TDO~reg0
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk0'
Slack          : 4.924 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg0
To             : rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg0
From Clock     : clk0
To Clock       : clk0
Failed Paths   : 0

Type           : Clock Setup: 'CNTT'
Slack          : 7.203 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : FREQTEST:121|CNT:U3|lpm_counter:lpm_counter_component|cntr_8f8:auto_generated|safe_q[0]
To             : FREQTEST:121|CNT:U3|lpm_counter:lpm_counter_component|cntr_8f8:auto_generated|safe_q[15]
From Clock     : CNTT
To Clock       : CNTT
Failed Paths   : 0

Type           : Clock Setup: 'clk5'
Slack          : 7.682 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : CNT5:132|lpm_counter:CQI_rtl_0|cntr_ds6:auto_generated|safe_q[1]
To             : CNT5:132|lpm_counter:CQI_rtl_0|cntr_ds6:auto_generated|safe_q[4]
From Clock     : clk5
To Clock       : clk5
Failed Paths   : 0

Type           : Clock Setup: 'D_STP'
Slack          : 8.273 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : DECD:136|CQ[0]
To             : DECD:136|CQ[1]
From Clock     : D_STP
To Clock       : D_STP
Failed Paths   : 0

Type           : Clock Setup: 'F1HZ'
Slack          : 8.711 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : FREQTEST:121|TESTCTL:U1|Div2CLK
To             : FREQTEST:121|TESTCTL:U1|Div2CLK
From Clock     : F1HZ
To Clock       : F1HZ
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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