step_a.map.rpt

步进的控制电机控制 c++环境下开发

Info: Found 2 design units, including 1 entities, in source file cnt.vhd
    Info: Found design unit 1: CNT-SYN
    Info: Found entity 1: CNT
Info: Found 2 design units, including 1 entities, in source file reg.vhd
    Info: Found design unit 1: REG-SYN
    Info: Found entity 1: REG
Info: Found 2 design units, including 1 entities, in source file testctl.vhd
    Info: Found design unit 1: TESTCTL-behav
    Info: Found entity 1: TESTCTL
Info: Found 2 design units, including 1 entities, in source file freqtest.vhd
    Info: Found design unit 1: FREQTEST-struc
    Info: Found entity 1: FREQTEST
Info: Found 2 design units, including 1 entities, in source file lcnt8.vhd
    Info: Found design unit 1: LCNT8-behav
    Info: Found entity 1: LCNT8
Info: Found 2 design units, including 1 entities, in source file dec1.vhd
    Info: Found design unit 1: Dec1-one
    Info: Found entity 1: Dec1
Info: Found 2 design units, including 1 entities, in source file dec2.vhd
    Info: Found design unit 1: Dec2-one
    Info: Found entity 1: Dec2
Warning: Can't analyze file -- file D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.gdf is missing
Info: Found 1 design units, including 1 entities, in source file step_a.bdf
    Info: Found entity 1: step_a
Warning: Found inconsistent dimensions
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/others/maxplus2/21mux.bdf
    Info: Found entity 1: 21mux
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/LPM_COMPARE.tdf
    Info: Found entity 1: lpm_compare
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/comptree.tdf
    Info: Found entity 1: comptree
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/cmpchain.tdf
    Info: Found entity 1: cmpchain
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: VHDL Case Statement information at decd.vhd(19): OTHERS choice is never selected
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/lpm_ff.tdf
    Info: Found entity 1: lpm_ff
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_8f8.tdf
    Info: Found entity 1: cntr_8f8
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/BUSMUX.tdf
    Info: Found entity 1: busmux
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/lpm_mux.tdf
    Info: Found entity 1: lpm_mux
Info: Found 1 design units, including 1 entities, in source file db/mux_6fc.tdf
    Info: Found entity 1: mux_6fc
Info: VHDL Case Statement information at dec2.vhd(19): OTHERS choice is never selected
Warning: VHDL Process Statement warning at cnt24.vhd(13): signal cqi is in statement, but is not in sensitivity list
Info: Using design file rom3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: rom3-SYN
    Info: Found entity 1: rom3
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_0fs.tdf
    Info: Found entity 1: altsyncram_0fs
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s6a2.tdf
    Info: Found entity 1: altsyncram_s6a2
Info: Found 3 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Found 2 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Found 6 design units, including 2 entities, in source file ../../../altera/quartus41/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf
    Info: Found entity 1: decode_9ie
Info: Found 2 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: CNT5:132|CQI[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: CNT8:83|CQI[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: CNT24:127|CQI[0]~25
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~200
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~10
Info: Found 1 design units, including 1 entities, in source file db/cntr_ds6.tdf
    Info: Found entity 1: cntr_ds6
Info: Found 1 design units, including 1 entities, in source file db/cntr_rq5.tdf
    Info: Found entity 1: cntr_rq5
Info: Found 1 design units, including 1 entities, in source file db/cntr_s98.tdf
    Info: Found entity 1: cntr_s98
Info: Found 1 design units, including 1 entities, in source file db/cntr_qd8.tdf
    Info: Found entity 1: cntr_qd8
Info: Registers with preset signals will power-up high
Info: Converted 15 single input CARRY primitives to CARRY_SUM primitives
Info: Implemented 313 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 26 output pins
    Info: Implemented 259 logic cells
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Sat Apr 23 11:36:33 2005
    Info: Elapsed time: 00:00:31