📄 step_a.map.rpt
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+--------------------------------------------------------------------+--------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 2:1 ; 5 bits ; 5 LEs ; 5 LEs ; 0 LEs ; Yes ; |step_a|CNT24:127|CQI[1] ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |step_a|BUSMUX:41|lpm_mux:$00000|mux_6fc:auto_generated|w_result49w~2 ;
; 2:1 ; 5 bits ; 5 LEs ; 5 LEs ; 0 LEs ; Yes ; |step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] ;
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 22:1 ; 4 bits ; 56 LEs ; 44 LEs ; 12 LEs ; Yes ; |step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 2:1 ; 5 bits ; 5 LEs ; 5 LEs ; 0 LEs ; Yes ; |step_a|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |step_a|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] ;
; 18:1 ; 4 bits ; 48 LEs ; 32 LEs ; 16 LEs ; Yes ; |step_a|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 80 ;
; Number of synthesis-generated cells ; 179 ;
; Number of WYSIWYG LUTs ; 80 ;
; Number of synthesis-generated LUTs ; 126 ;
; Number of WYSIWYG registers ; 64 ;
; Number of synthesis-generated registers ; 99 ;
; Number of cells with combinational logic only ; 96 ;
; Number of cells with registers only ; 53 ;
; Number of cells with combinational logic and registers ; 110 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear ; 5 ;
; Number of registers using Synchronous Load ; 28 ;
; Number of registers using Asynchronous Clear ; 88 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 79 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Setting ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode ; Hierarchy Location ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------+
; 0 ; rom4 ; 16 ; 32 ; Read/Write ; |step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------+
+-----------+
; Hierarchy ;
+-----------+
step_a
|-- busmux:41
|-- lpm_mux:$00000
|-- mux_6fc:auto_generated
|-- 21mux:65
|-- 21mux:66
|-- CNT8:83
|-- lpm_counter:CQI_rtl_1
|-- cntr_ds6:auto_generated
|-- cmp3:93
|-- lpm_compare:1
|-- altshift:aeb_ext_lat_ffs
|-- altshift:agb_ext_lat_ffs
|-- comptree:comparator
|-- cmpchain:cmp_end
|-- cmp3:94
|-- lpm_compare:1
|-- altshift:aeb_ext_lat_ffs
|-- altshift:agb_ext_lat_ffs
|-- comptree:comparator
|-- cmpchain:cmp_end
|-- cmp3:95
|-- lpm_compare:1
|-- altshift:aeb_ext_lat_ffs
|-- altshift:agb_ext_lat_ffs
|-- comptree:comparator
|-- cmpchain:cmp_end
|-- cmp3:96
|-- lpm_compare:1
|-- altshift:aeb_ext_lat_ffs
|-- altshift:agb_ext_lat_ffs
|-- comptree:comparator
|-- cmpchain:cmp_end
|-- FREQTEST:121
|-- TESTCTL:U1
|-- REG:U2
|-- lpm_ff:lpm_ff_component
|-- CNT:U3
|-- lpm_counter:lpm_counter_component
|-- cntr_8f8:auto_generated
|-- Dec2:125
|-- CNT24:127
|-- lpm_counter:CQI_rtl_2
|-- cntr_rq5:auto_generated
|-- cmp3:131
|-- lpm_compare:1
|-- altshift:aeb_ext_lat_ffs
|-- altshift:agb_ext_lat_ffs
|-- comptree:comparator
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