sysinit.c

CodeWarrior IDE!COLDFIRE 5275源程序!

/*
 * File:		sysinit.c
 * Purpose:		Reset configuration of the M5275EVB
 *
 * Notes:		
 */

#include "src/init/m5275evb.h"

/********************************************************************/

void mcf5275_init(void);
void mcf5275_wtm_init(void);
void mcf5275_pll_init(void);
void mcf5275_uart_init(void);
void mcf5275_scm_init(void);
void mcf5275_gpio_init(void);
void mcf5275_cs_init(void);
void mcf5275_sdram_init(void);

/********************************************************************/
void
mcf5275_init(void)
{
	extern char __DATA_ROM[];
	extern char __DATA_RAM[];
	extern char __DATA_END[];
	extern char __BSS_START[];
	extern char __BSS_END[];
	extern uint32 VECTOR_TABLE[];
	extern uint32 __VECTOR_RAM[];
	register uint32 n;
	register uint8 *dp, *sp;

	mcf5275_wtm_init();
	mcf5275_pll_init();
	mcf5275_gpio_init();
	mcf5275_scm_init();
	mcf5275_uart_init();
	mcf5275_cs_init();
	mcf5275_sdram_init();
	
	/* Turn Instruction Cache ON */
	mcf5xxx_wr_cacr(0
		| MCF5XXX_CACR_CENB
		| MCF5XXX_CACR_CINV
		| MCF5XXX_CACR_DISD
		| MCF5XXX_CACR_CEIB
		| MCF5XXX_CACR_CLNF_00);
	
		
	/* Copy the vector table to RAM */
	if (__VECTOR_RAM != VECTOR_TABLE)
	{
		for (n = 0; n < 256; n++)
			__VECTOR_RAM[n] = VECTOR_TABLE[n];
	}
	mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);

	/* 
	 * Move initialized data from ROM to RAM. 
	 */
	if (__DATA_ROM != __DATA_RAM)
	{
		dp = (uint8 *)__DATA_RAM;
		sp = (uint8 *)__DATA_ROM;
		n = __DATA_END - __DATA_RAM;
		while (n--)
			*dp++ = *sp++;
	}
 
	/* 
	 * Zero uninitialized data 
	 */
	if (__BSS_START != __BSS_END)
	{
		sp = (uint8 *)__BSS_START;
		n = __BSS_END - __BSS_START;
		while (n--)
			*sp++ = 0;
	}
}
/********************************************************************/
void 
mcf5275_wtm_init(void)
{
	/*
	 * Disable Software Watchdog Timer
	 */
	MCF_WTM_WCR = 0;
}
/********************************************************************/
void 
mcf5275_pll_init(void)
{
	uint32 temp;
	/*
	 * Multiply 25Mhz reference crystal to acheive system clock of 150Mhz
	 */
	
	MCF_FMPLL_SYNCR = MCF_FMPLL_SYNCR_MFD(1) | MCF_FMPLL_SYNCR_RFD(0);
	
	while (!(MCF_FMPLL_SYNSR & MCF_FMPLL_SYNSR_LOCK));
}
/********************************************************************/
void
mcf5275_scm_init(void)
{
	/* 
	 * Enable on-chip modules to access internal SRAM 
	 */
	MCF_SCM_RAMBAR = (0 
		| MCF_SCM_RAMBAR_BA(SRAM_ADDRESS>>16)
		| MCF_SCM_RAMBAR_BDE);
}
/********************************************************************/
void 
mcf5275_gpio_init(void)
{
	uint8 temp;
	
	/* 
	 * Initialize PAR to enable SDRAM signals 
	 */	
	MCF_GPIO_PAR_SDRAM = 0x03FF;
	
	/* 
	 * Initialize PAR to enable Ethernet signals 
	 */
	MCF_GPIO_PAR_FECI2C = 0xF0;
	
	/* 
	 * Set Port UA to initialize URXD0/URXD1/URXD2 UTXD0/UTXD1/UTXD2 
	 */
	MCF_GPIO_PAR_UART = 0x3FFF;		
	

}
/********************************************************************/
void
mcf5275_uart_init(void)
{
	/*
	 * Initialize all three UARTs for serial communications
	 */

	register uint16 ubgs;
	


	/* 
	 * Reset Transmitter 
	 */
	MCF_UART_UCR0 = MCF_UART_UCR_RESET_TX;
	MCF_UART_UCR1 = MCF_UART_UCR_RESET_TX;
	MCF_UART_UCR2 = MCF_UART_UCR_RESET_TX;

	/* 
	 * Reset Receiver 
	 */
	MCF_UART_UCR0 = MCF_UART_UCR_RESET_RX;
	MCF_UART_UCR1 = MCF_UART_UCR_RESET_RX;
	MCF_UART_UCR2 = MCF_UART_UCR_RESET_RX;

	/* 
	 * Reset Mode Register 
	 */
	MCF_UART_UCR0 = MCF_UART_UCR_RESET_MR;
	MCF_UART_UCR1 = MCF_UART_UCR_RESET_MR;
	MCF_UART_UCR2 = MCF_UART_UCR_RESET_MR;

	/* 
	 * No parity, 8-bits per character 
	 */
	MCF_UART_UMR0 = (0
		| MCF_UART_UMR_PM_NONE
		| MCF_UART_UMR_BC_8 );
	MCF_UART_UMR1 = (0
		| MCF_UART_UMR_PM_NONE
		| MCF_UART_UMR_BC_8 );
	MCF_UART_UMR2 = (0
		| MCF_UART_UMR_PM_NONE
		| MCF_UART_UMR_BC_8 );

	/* 
	 * No echo or loopback, 1 stop bit 
	 */
	MCF_UART_UMR0 = (0
		| MCF_UART_UMR_CM_NORMAL
		| MCF_UART_UMR_SB_STOP_BITS_1);
	MCF_UART_UMR1 = (0
		| MCF_UART_UMR_CM_NORMAL
		| MCF_UART_UMR_SB_STOP_BITS_1);
	MCF_UART_UMR2 = (0
		| MCF_UART_UMR_CM_NORMAL
		| MCF_UART_UMR_SB_STOP_BITS_1);

	/* 
	 * Set Rx and Tx baud by timer 
	 */
	MCF_UART_UCSR0 = (0
		| MCF_UART_UCSR_RCS_SYS_CLK
		| MCF_UART_UCSR_TCS_SYS_CLK);
	MCF_UART_UCSR1 = (0
		| MCF_UART_UCSR_RCS_SYS_CLK
		| MCF_UART_UCSR_TCS_SYS_CLK);
	MCF_UART_UCSR2 = (0
		| MCF_UART_UCSR_RCS_SYS_CLK
		| MCF_UART_UCSR_TCS_SYS_CLK);

	/* 
	 * Mask all UART interrupts 
	 */
	MCF_UART_UIMR0 = 0;
	MCF_UART_UIMR1 = 0;
	MCF_UART_UIMR2 = 0;
                 
	/* 
	 * Calculate baud settings 
	 */
	ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));

	MCF_UART_UBG1(0) = (uint8)((ubgs & 0xFF00) >> 8);
	MCF_UART_UBG2(0) = (uint8)(ubgs & 0x00FF);
	MCF_UART_UBG1(1) = (uint8)((ubgs & 0xFF00) >> 8);
	MCF_UART_UBG2(1) = (uint8)(ubgs & 0x00FF);
	MCF_UART_UBG1(2) = (uint8)((ubgs & 0xFF00) >> 8);
	MCF_UART_UBG2(2) = (uint8)(ubgs & 0x00FF);

	/* 
	 * Enable receiver and transmitter 
	 */
	MCF_UART_UCR0 = (0
		| MCF_UART_UCR_TX_ENABLED
		| MCF_UART_UCR_RX_ENABLED);
	MCF_UART_UCR1 = (0
		| MCF_UART_UCR_TX_ENABLED
		| MCF_UART_UCR_RX_ENABLED);
	MCF_UART_UCR2 = (0
		| MCF_UART_UCR_TX_ENABLED
		| MCF_UART_UCR_RX_ENABLED);

}
/********************************************************************/
void
mcf5275_sdram_init(void)
{

	/* Initialize DDR on the M5275EVB board */
	
	/*
	 * Check to see if the SDRAM has already been initialized
	 * by a run control tool
	 */
	if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
	{

		/* Initialize SDRAM chip select */
        MCF_SDRAMC_SDBAR0 = (0
            | MCF_SDRAMC_SDBARn_BASE(SDRAM_ADDRESS)
            );
            
		MCF_SDRAMC_SDMR0 = (0
			| MCF_SDRAMC_SDMRn_BAM_32M
			| MCF_SDRAMC_SDMRn_V
			);            

		/* Initialize timing parameters */
		MCF_SDRAMC_SDCFG1 = 0x83711630;
		MCF_SDRAMC_SDCFG2 = 0x46770000;		
            
		/* Enable clock and write to SDMR */
		MCF_SDRAMC_SDCR = (0
			| MCF_SDRAMC_SDCR_MODE_EN
			| MCF_SDRAMC_SDCR_CKE
   		 	);
   	   		
   		/* Set IPALL bit */ 	
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;		   		 	
   		 	
		/* Dummy write to SDRAM to issue PALL */
		*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
		
		
		/* Write extended mode register */
		MCF_SDRAMC_SDMR = (0
			| MCF_SDRAMC_SDMR_BNKAD_LEMR
			| MCF_SDRAMC_SDMR_AD(0x0)
			| MCF_SDRAMC_SDMR_CMD        
            );
                    
		/* Dummy write to SDRAM to issue LEMR */
		*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
        
		/* Write mode register and reset DLL */
        MCF_SDRAMC_SDMR = 0x058D0000;
                         
		/* Dummy write to SDRAM to issue LMR */
		*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
		
		/* Clear SDMR CMD bit to stop issuing LMR/LEMR commands */
		MCF_SDRAMC_SDMR &= ~(MCF_SDRAMC_SDMR_CMD);    
    		
		/* Execute a PALL command */
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
				
		/* Dummy write to SDRAM to issue PALL */
		*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
 		
 		/* Clear IPALL bit to stop issuing PALL commands */
 		MCF_SDRAMC_SDCR &= ~(MCF_SDRAMC_SDCR_IPALL);
 		 
			/* Perform two REF cycles */
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
		
		/* Dummy write to SDRAM to issue first REF */
		*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;

		/* Dummy write to SDRAM to issue second REF */
		*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
	
		/* Write mode register and clear reset DLL */
        MCF_SDRAMC_SDMR = 0x018D0000;
				
		/* Dummy write to SDRAM to issue LMR */
		*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
		
		/* Clear SDMR CMD bit to stop issuing LMR/LEMR commands */
		MCF_SDRAMC_SDMR &= ~(MCF_SDRAMC_SDMR_CMD);
		
		MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;		 
		
		/* Enable auto refresh and lock SDMR */
		MCF_SDRAMC_SDCR = (0
			| MCF_SDRAMC_SDCR_CKE
			| MCF_SDRAMC_SDCR_REF
			| MCF_SDRAMC_SDCR_MUX(1)
			| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) /* 1 added to round up */
			| MCF_SDRAMC_SDCR_DQS_OE(0x3) 
            );
            
	}
}
/********************************************************************/
void
mcf5275_cs_init(void)
{
	/* 
	 * ChipSelect 1 - External SRAM 
	 */
	MCF_CS_CSAR1 = MCF_CS_CSAR_BA(EXT_SRAM_ADDRESS);
	MCF_CS_CSCR1 = (0
		| MCF_CS_CSCR_IWS(6)
		| MCF_CS_CSCR_AA
		| MCF_CS_CSCR_PS_32);
	
	MCF_CS_CSMR1 = MCF_CS_CSMR_BAM_1M | MCF_CS_CSMR_V;
    
    /* 
	 * ChipSelect 0 - External Flash 
	 */ 
	MCF_CS_CSAR0 = MCF_CS_CSAR_BA(EXT_FLASH_ADDRESS);
	MCF_CS_CSCR0 = (0
		| MCF_CS_CSCR_IWS(6)
		| MCF_CS_CSCR_AA
		| MCF_CS_CSCR_PS_16);
	MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
}
/********************************************************************/