lh79524_eth.h

网络驱动程序

/***********************************************************************
* $Workfile:   lh79524_eth.h  $
* $Revision:   1.0  $
* $Author:   ZhangJ  $
* $Date:   Oct 20 2004 10:38:12  $
*
* Project: LH79524 headers
*
* Description:
*      This file contains the structure definitions and manifest
*      constants for LH79524 component:
*          Ethernet MAC
*
* Revision History:
* $Log::   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps$
 * 
 *    Rev 1.0   Oct 20 2004 10:38:12   ZhangJ
 * Initial revision.
 * 
 *    Rev 1.0   Jul 21 2004 15:35:34   PattamattaD
 * Initial revision.
* 
*
*
***********************************************************************
* 
*  Copyright (c) 2004 Sharp Microelectronics of the Americas 
* 
*  All rights reserved 
* 
*  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION 
*  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE, 
*  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
*  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE. 
* 
*  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
*  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
*  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE 
*  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS. 
* 
**********************************************************************/

#ifndef LH79524_ETH_H
#define LH79524_ETH_H

/***********************************************************************
* Ethernet MAC Module Register Structure
**********************************************************************/
#ifndef __ASSEMBLY__
/* The Address organisation for the MAC device.  All addresses are split into
* two 32-bit register fields.  The first one (bottom) is the lower 32-bits of
* the address and the other field are the high order bits - this may be 16-bits
* in the case of MAC addresses, or 32-bits for the hash address.
* In terms of memory storage, the first item (bottom) is assumed to be at a
* lower address location than 'top'. i.e. top should be at address location of
* 'bottom' + 4 bytes.
*/
typedef struct {
  UNS_32  bottom;     /* Lower 32-bits of address. */
  UNS_32  top;        /* Upper 32-bits of address. */
} MAC_ADDR_T;


/* The set of statistics registers implemented in the LH79524 MAC.
* The statistics registers implemented are a subset of all the statistics
* available, but contains all the compulsory ones.
* For full descriptions on the registers, refer to the LH79524 MAC programmers
* guide or the IEEE 802.3 specifications.
*/
typedef struct {
  UNS_32  pause_rx;           /* Number of pause frames received. */
  UNS_32  frames_tx;          /* Number of frames transmitted OK */
  UNS_32  single_col;         /* Number of single collision frames */
  UNS_32  multi_col;          /* Number of multi collision frames */
  UNS_32  frames_rx;          /* Number of frames received successfully */
  UNS_32  fcs_errors;         /* Number of frames received with crc errors */
  UNS_32  align_errors;       /* Frames received without integer no. bytes */
  UNS_32  def_tx;             /* Frames deferred due to crs */
  UNS_32  late_col;           /* Collisions occuring after slot time */
  UNS_32  excess_col;         /* Number of excessive collision frames. */
  UNS_32  tx_urun;            /* Transmit underrun errors due to DMA */
  UNS_32  crs_errors;         /* Errors caused by crs not being asserted. */
  UNS_32  rx_res_errors;      /* Number of times buffers ran out during rx */
  UNS_32  rx_orun;            /* Receive overrun errors due to DMA */
  UNS_32  rx_symbol_errors;   /* Number of times rx_er asserted during rx */
  UNS_32  excess_length;      /* Number of excessive length frames rx */
  UNS_32  jabbers;            /* Excessive length + crc or align errors. */
  UNS_32  usize_frames;       /* Frames received less than min of 64 bytes */
  UNS_32  sqe_errors;         /* Number of times col was not asserted */
  UNS_32  length_check_errors;/* Number of frames with incorrect length */
  UNS_32  pause_tx;           /* Number of pause frames transmitted. */
  
} MAC_STATS_T;


/* This is the memory map for the LH79524 Enhanced MAC device.
* For full descriptions on the registers, refer to the LH79524 MAC programmers
* guide or the IEEE 802.3 specifications.
*/
typedef struct {
  volatile UNS_32  net_control;      /* Network control 0x00 */
  volatile UNS_32  net_config;       /* Network config 0x04 */
  const volatile UNS_32  net_status; /* Network status, RO, 0x08 */
  const volatile UNS_32  rsvd0;      /* reserved 0x0C*/
  const volatile UNS_32  rsvd1;      /* reserved 0x10*/
  volatile UNS_32  tx_status;        /* Transmit status 0x14 */
  volatile UNS_32  rx_qptr;          /* Receive queue pointer 0x18 */
  volatile UNS_32  tx_qptr;          /* Transmit queue pointer 0x1C */
  volatile UNS_32  rx_status;        /* Receive status 0x20 */
  volatile UNS_32  irq_status;       /* Interrupt status 0x24 */
  volatile UNS_32  irq_enable;       /* Interrupt enable 0x28 */
  volatile UNS_32  irq_disable;      /* Interrupt disable 0x2C */
  const volatile UNS_32 irq_mask;    /* Interrupt mask, RO, 0x30 */
  volatile UNS_32  phy_man;          /* PHY management 0x34 */
  const volatile UNS_32  pause_time; /* Pause time register 0x38 */
  volatile MAC_STATS_T stats;        /* MAC statistics 0x3C - 0x8C */
  volatile MAC_ADDR_T hash_addr;     /* Hash address 0x90 - 0x94 */
  volatile MAC_ADDR_T spec_addr_1;   /* Specific address 1. 0x98 - */
  volatile MAC_ADDR_T spec_addr_2;   /* Specific address 2. */
  volatile MAC_ADDR_T spec_addr_3;   /* Specific address 3. */
  volatile MAC_ADDR_T spec_addr_4;   /* Specific address 4. - 0xB4 */
  volatile UNS_32  id_check;         /* Type ID check 0xB8 */
  volatile UNS_32  tx_pause_quant;   /* Transmit pause quantum. 0xBC*/
  volatile UNS_32  user_io;          /* User IO register, 0xC0 */
  /* 0xC4 to 0xF8 reserved not listed to save */
  /* space, Rev_id in 0xFC, not listed. */
} ETHERNET_REGS_T, *PETHERNET_REGS_T;

/* Define the structure for each queue element in the receive buffers descriptor
* queue list.
* These are the structures that hold information on where the storage buffer
* for received frames are held and also contain status information after a
* frame has been successfully received.
* The rx_qptr register in the MAC_REG structure points to the first of these
* buffer descriptors, the complete list of buffer descriptors specify all the
* information required for the MAC to store incoming frames at the appropriate
* location in memory.
* The structure consists of two 32-bit registers, the first - word0 contains a
* 32-bit word aligned address pointing to the address of the buffer.
* The lower two bits make up the wrap bit indicating the last descriptor and
* the ownership bit to indicate it has been used by the MAC.
* The following register - word1, contains status information regarding why the
* frame was received (the filter match condition) as well as other useful info.
* Both registers have been declared so that they can be accessed as a 32-bit
* value via their 'reg' field, or access each individual bit using the 'bits'
* field.
*/
typedef struct {
  volatile UNS_32 word0;
  volatile UNS_32 word1; /* Will only be updated by MAC */
} RX_BUFF_T;             /* Receive Buffer Queue Element */


/* Define the structure for each queue element in the transmit buffers descriptor
* queue list.
* These are the structures that hold information on where the storage buffer
* for frames to be transmitted are held and also contain status information on
* whether the frame has been successfully transmitted or indicate why not.
* The tx_qptr register in the MAC_REG structure points to the first of these
* buffer descriptors, the complete list of buffer descriptors specify all the
* information required for the MAC to transmit frames in sequence, starting
* with the first descriptor.
* The structure consists of two 32-bit registers, the first - word0 contains a
* 32-bit address pointing to the location of the transmit data.
* The following register - word1, consists of various information to control
* the MAC transmit process.  After transmit, this is updated with status
* information, whether the frame was transmitted OK or why it had failed.
* 'word1' has been declared so that it can be accessed as a 32-bit value via
* its 'reg' field, or can access each individual bit using the 'bits' field.
*/
typedef struct {
  volatile UNS_32  word0; /* 32-bit transmit buffer address */
  volatile UNS_32  word1;
} TX_BUFF_T;              /* Transmit Buffer Queue Element */

#endif /*__ASSEMBLY__ */

/* Define some memory offsets for easier direct access to memory map. */
#define ETH_NET_CONTROL_OFFSET         (0x00)
#define ETH_NET_CONFIG_OFFSET          (0x04)
#define ETH_NET_STATUS_OFFSET          (0x08)
#define ETH_TX_STATUS_OFFSET           (0x14)
#define ETH_RX_QPTR_OFFSET             (0x18)