95sport2-1.lst

PIC18系列与RF315MHz连接透过RF传输数值资料

                                           #define DATA		LATB                                                               D:\gary\work\mplab\95sport\95sport2-1.c
                                                                                                                            D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define NUMBER_SPACE	10                                                          D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define NORMAL	0                                                                 D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define PLAYER	1                                                                 D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define TRUE	1                                                                   D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define FAULT	0                                                                  D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define NO_KEY_PRESSED	0                                                         D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define SETTING_KEY		1                                                           D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define SET_MODE_KEY	2                                                           D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define CLEAR_KEY		3                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define ON_OFF_KEY		4                                                            D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define RF_TR_ENABLE	0                                                           D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define RF_TR_DISABLE	1                                                          D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define START_CHAR		0xaa                                                         D:\gary\work\mplab\95sport\95sport2-1.c
                                                                                                                            D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define bit_sport_mode				flag1.bit0                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define bit_sandbag_kg_set			flag1.bit1                                          D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define bit_sandbag_location_set	flag1.bit2                                      D:\gary\work\mplab\95sport\95sport2-1.c
                                           #define bit_check_even				flag1.bit5                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                                                                                                            D:\gary\work\mplab\95sport\95sport2-1.c
                                           void isr_high_code(void);                                                        D:\gary\work\mplab\95sport\95sport2-1.c
                                           void isr_high(void);                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                           void mcu_io_init(void);                                                          D:\gary\work\mplab\95sport\95sport2-1.c
                                           void init_val(void);                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                           void bcd_to_bin(void);                                                           D:\gary\work\mplab\95sport\95sport2-1.c
                                                                                                                            D:\gary\work\mplab\95sport\95sport2-1.c
                                           typedef struct                                                                   D:\gary\work\mplab\95sport\95sport2-1.c
                                           {                                                                                D:\gary\work\mplab\95sport\95sport2-1.c
                                           	unsigned bit0:1;                                                                D:\gary\work\mplab\95sport\95sport2-1.c
                                               unsigned bit1:1;                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                               unsigned bit2:1;                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                               unsigned bit3:1;                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                               unsigned bit4:1;                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                               unsigned bit5:1;                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                               unsigned bit6:1;                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                               unsigned bit7:1;                                                             D:\gary\work\mplab\95sport\95sport2-1.c
                                           }uns8_flag;                                                                      D:\gary\work\mplab\95sport\95sport2-1.c
                                           uns8_flag flag1;                                                                 D:\gary\work\mplab\95sport\95sport2-1.c
                                                                                                                            D:\gary\work\mplab\95sport\95sport2-1.c
                                           uns8 i,rf_re_buf,rf_re_buf_bak,rx_high8,rx_low8,receive_count,check_num,check_num_bak,check_sum; D:\gary\work\mplab\95sport\95sport2-1.c
                                           uns16 kg;                                                                        D:\gary\work\mplab\95sport\95sport2-1.c
                                                                                                                            D:\gary\work\mplab\95sport\95sport2-1.c
                                           #pragma code hi_vector=0x0008                                                    D:\gary\work\mplab\95sport\95sport2-1.c
                                           void isr_high_code(void)                                                         D:\gary\work\mplab\95sport\95sport2-1.c
                                           {                                                                                D:\gary\work\mplab\95sport\95sport2-1.c
                                           	_asm                                                                            D:\gary\work\mplab\95sport\95sport2-1.c
000008   ef16     GOTO      0x2c           		goto	isr_high                                                                  D:\gary\work\mplab\95sport\95sport2-1.c
00000a   f000                                                                                                               
                                           	_endasm                                                                         D:\gary\work\mplab\95sport\95sport2-1.c
00000c   0012     RETURN    0x0            }                                                                                D:\gary\work\mplab\95sport\95sport2-1.c
                                           #pragma code	/* return to the default code section */                            D:\gary\work\mplab\95sport\95sport2-1.c
                                                                                                                            D:\gary\work\mplab\95sport\95sport2-1.c
                                           #pragma interrupt isr_high //save=PROD//,section(".tmpdata"),TABLAT,TBLPTR,PCLATH,PCLATU D:\gary\work\mplab\95sport\95sport2-1.c
00002c   cfda     MOVFF     0xfda,0xfe4    void isr_high(void)                                                              D:\gary\work\mplab\95sport\95sport2-1.c
00002e   ffe4                                                                                                               
000030   cfe2     MOVFF     0xfe2,0xfda                                                                                     
000032   ffda                                                                                                               
000034   52e6     MOVF      0xe6,0x1,0x0                                                                                    
                                           {                                                                                D:\gary\work\mplab\95sport\95sport2-1.c
000036   50f2     MOVF      0xf2,0x0,0x0   	if(TMR0IF && TMR0IE)	//Timer0 interrupt,1ms interrupt one time                  D:\gary\work\mplab\95sport\95sport2-1.c
000038   0b04     ANDLW     0x4                                                                                             
00003a   e004     BZ        0x44                                                                                            
00003c   50f2     MOVF      0xf2,0x0,0x0                                                                                    
00003e   0b20     ANDLW     0x20                                                                                            
000040   e001     BZ        0x44                                                                                            
                                           	{                                                                               D:\gary\work\mplab\95sport\95sport2-1.c
000042   94f2     BCF       0xf2,0x2,0x0   		TMR0IF=0;                                                                      D:\gary\work\mplab\95sport\95sport2-1.c
                                           	}                                                                               D:\gary\work\mplab\95sport\95sport2-1.c
000044   509d     MOVF      0x9d,0x0,0x0   	if(ADIE && ADIF)                                                                D:\gary\work\mplab\95sport\95sport2-1.c
000046   0b40     ANDLW     0x40                                                                                            
000048   e004     BZ        0x52                                                                                            
00004a   509e     MOVF      0x9e,0x0,0x0                                                                                    
00004c   0b40     ANDLW     0x40                                                                                            
00004e   e001     BZ        0x52                                                                                            
                                           	{                                                                               D:\gary\work\mplab\95sport\95sport2-1.c
000050   9c9e     BCF       0x9e,0x6,0x0   		ADIF=0;                                                                        D:\gary\work\mplab\95sport\95sport2-1.c
                                           	}                                                                               D:\gary\work\mplab\95sport\95sport2-1.c
000052   509d     MOVF      0x9d,0x0,0x0   	if(TMR1IE && TMR1IF)                                                            D:\gary\work\mplab\95sport\95sport2-1.c
000054   0b01     ANDLW     0x1                                                                                             
000056   e004     BZ        0x60                                                                                            
000058   509e     MOVF      0x9e,0x0,0x0                                                                                    
00005a   0b01     ANDLW     0x1                                                                                             
00005c   e001     BZ        0x60                                                                                            
                                           	{                                                                               D:\gary\work\mplab\95sport\95sport2-1.c