ryxiangwei.v

数字相位计实现

module ryxiangwei(clk,Rxd,Txd,out_addr,
        Load,gate       );     //,out_11,out_111,out_43210,out_40,mode,reset

input  clk;//,reset;
input  Rxd,Txd;

input  Load;

output  gate;
output  out_addr;

reg [7:0] out_addr;

reg [23:0]add_num;

reg  [15:0]out_link;
reg  [16:0]out_link_link;
reg  [7:0]out_link_link1;
reg  [7:0]gate;
//reg  clk1;
//reg  [3:0]fp;
wire Load;


wire Rxd,Txd;



always @(negedge Txd)
  begin
    out_link_link={out_link_link[15:0],Rxd};
  
  end

always @(posedge clk)
 begin

     
           if(!Load)
              begin
                  if (out_link_link[16]==0)
                  out_link=out_link_link[15:0];
                  add_num = 24'b0000_0000_0000_0000_0000_0000;
               
                  if (out_link_link[16]==1)
                   out_link_link1=out_link_link[7:0];
                   add_num = 24'b0000_0000_0000_0000_0000_0000;
               
              end
                    
           else
              begin
              
                 
                       add_num=add_num+out_link;
                       gate=add_num[23:16];
                       out_addr=gate+out_link_link1;
                    //   if (gate+out_link_link1>=8'b10110100)
                    //     out_addr=gate+out_link_link1-8'b01011010;
                    //   if(gate==8'b10110100)
                    //     add_num[23:16]=8'b00000000;
                       
                 
         end
   end
endmodule