ryxiangwei_v.sdo

来自「数字相位计实现」· SDO 代码 · 共 1,694 行 · 第 1/5 页

SDO
1,694 行
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    (DELAY
      (ABSOLUTE
        (PORT pclk[0] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge pclk[0]) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (4000:4000:4000))
      (HOLD datain (posedge pclk[0]) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link_link\[11\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link_link\[11\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT pclk[0] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge pclk[0]) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (4000:4000:4000))
      (HOLD datain (posedge pclk[0]) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link_link\[12\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link_link\[12\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT pclk[0] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge pclk[0]) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (4000:4000:4000))
      (HOLD datain (posedge pclk[0]) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link_link\[13\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link_link\[13\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT pclk[0] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge pclk[0]) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (4000:4000:4000))
      (HOLD datain (posedge pclk[0]) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link_link\[14\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link_link\[14\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT pclk[0] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge pclk[0]) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (4000:4000:4000))
      (HOLD datain (posedge pclk[0]) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link_link\[15\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link_link\[15\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT pclk[0] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge pclk[0]) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (4000:4000:4000))
      (HOLD datain (posedge pclk[0]) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link_link\[16\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link_link\[16\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT pclk[0] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge pclk[0]) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (4000:4000:4000))
      (HOLD datain (posedge pclk[0]) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link_link1\[7\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link_link1\[7\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (0:0:0) (0:0:0))
        (PORT pena[0] (8000:8000:8000) (8000:8000:8000))
        (PORT pena[1] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (4000:4000:4000))
      (SETUP pena[0] (posedge clk) (4000:4000:4000))
      (SETUP pena[1] (posedge clk) (4000:4000:4000))
      (HOLD datain (posedge clk) (4000:4000:4000))
      (HOLD pena[0] (posedge clk) (4000:4000:4000))
      (HOLD pena[1] (posedge clk) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link\[7\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link\[7\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (0:0:0) (0:0:0))
        (PORT pena[0] (8000:8000:8000) (8000:8000:8000))
        (PORT pena[1] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (4000:4000:4000))
      (SETUP pena[0] (posedge clk) (4000:4000:4000))
      (SETUP pena[1] (posedge clk) (4000:4000:4000))
      (HOLD datain (posedge clk) (4000:4000:4000))
      (HOLD pena[0] (posedge clk) (4000:4000:4000))
      (HOLD pena[1] (posedge clk) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link\[3\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link\[3\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (0:0:0) (0:0:0))
        (PORT pena[0] (8000:8000:8000) (8000:8000:8000))
        (PORT pena[1] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (4000:4000:4000))
      (SETUP pena[0] (posedge clk) (4000:4000:4000))
      (SETUP pena[1] (posedge clk) (4000:4000:4000))
      (HOLD datain (posedge clk) (4000:4000:4000))
      (HOLD pena[0] (posedge clk) (4000:4000:4000))
      (HOLD pena[1] (posedge clk) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link\[0\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link\[0\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (0:0:0) (0:0:0))
        (PORT pena[0] (8000:8000:8000) (8000:8000:8000))
        (PORT pena[1] (8000:8000:8000) (8000:8000:8000))
        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (4000:4000:4000))
      (SETUP pena[0] (posedge clk) (4000:4000:4000))
      (SETUP pena[1] (posedge clk) (4000:4000:4000))
      (HOLD datain (posedge clk) (4000:4000:4000))
      (HOLD pena[0] (posedge clk) (4000:4000:4000))
      (HOLD pena[1] (posedge clk) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE add_num\[0\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (PORT pterm1[1] (2000:2000:2000) (2000:2000:2000))
        (PORT pterm1[2] (2000:2000:2000) (2000:2000:2000))
        (PORT pterm2[0] (2000:2000:2000) (2000:2000:2000))
        (PORT pterm2[1] (2000:2000:2000) (2000:2000:2000))
        (PORT pterm2[2] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH pterm1[1] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH pterm1[2] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH pterm2[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH pterm2[1] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH pterm2[2] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE add_num\[0\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (0:0:0) (0:0:0))
        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (4000:4000:4000))
      (HOLD datain (posedge clk) (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE out_link\[1\]\~I.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (2000:2000:2000) (2000:2000:2000))
        (IOPATH pterm1[0] regin (6000:6000:6000) (6000:6000:6000))
        (IOPATH fbkin regin (8000:8000:8000) (8000:8000:8000))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE out_link\[1\]\~I.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (0:0:0) (0:0:0))
        (PORT pena[0] (8000:8000:8000) (8000:8000:8000))
        (PORT pena[1] (8000:8000:8000) (8000:8000:8000))
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ryxiangwei_v.sdo - 源码说明

本页面展示了「数字相位计实现」中的 ryxiangwei_v.sdo 源码文件，采用 SDO 编程语言编写，共 1,694 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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