ryxiangwei.vo

数字相位计实现

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.0 Build 190 1/28/2004 SJ Full Version"

// DATE "11/01/2004 22:58:51"

// 
// Device: Altera EPM7128SLC84-15 Package PLCC84
// 

// 
// This Verilog file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

`timescale 1 ps/ 1 ps

module 	ryxiangwei (
	clk,
	Load,
	Txd,
	Rxd,
	out_addr,
	gate);
input 	clk;
input 	Load;
input 	Txd;
input 	Rxd;
output 	[7:0] out_addr;
output 	[7:0] gate;

supply0 gnd;
supply1 vcc;

// synopsys translate_off
initial $sdf_annotate("ryxiangwei_v.sdo");
// synopsys translate_on

wire \clk~dataout ;
wire \Rxd~dataout ;
wire \Txd~dataout ;
wire \out_link_link[0] ;
wire \out_link_link[1] ;
wire \out_link_link[2] ;
wire \out_link_link[3] ;
wire \out_link_link[4] ;
wire \out_link_link[5] ;
wire \out_link_link[6] ;
wire \out_link_link[7] ;
wire \Load~dataout ;
wire \out_link_link[8] ;
wire \out_link_link[9] ;
wire \out_link_link[10] ;
wire \out_link_link[11] ;
wire \out_link_link[12] ;
wire \out_link_link[13] ;
wire \out_link_link[14] ;
wire \out_link_link[15] ;
wire \out_link_link[16] ;
wire \out_link_link1[7] ;
wire \out_link[7] ;
wire \out_link[3] ;
wire \out_link[0] ;
wire \add_num[0] ;
wire \out_link[1] ;
wire \i89~8 ;
wire \add_num[1] ;
wire \out_link[2] ;
wire \i_rtl_1|adder[0]|unreg_res_node[2]~126 ;
wire \i_rtl_1|adder[0]|bg_out~32 ;
wire \i_rtl_1|adder[0]|unreg_res_node[2]~128 ;
wire \add_num[2] ;
wire \i_rtl_1|adder[0]|bg_out~33 ;
wire \i_rtl_1|adder[0]|gc[2]~42 ;
wire \i_rtl_1|adder[0]|g3~3 ;
wire \add_num[3] ;
wire \i_rtl_1|adder[0]|bg_out~31 ;
wire \i_rtl_1|adder[0]|g4~8 ;
wire \out_link[4] ;
wire \add_num[4] ;
wire \i_rtl_1|adder[0]|bg_out~30 ;
wire \i_rtl_1|adder[0]|p2c[0]~43 ;
wire \out_link[5] ;
wire \i_rtl_1|adder[0]|gn[4]~122sexp ;
wire \add_num[5] ;
wire \i_rtl_1|adder[0]|bg_out~29 ;
wire \i_rtl_1|adder[0]|p2c[2]~34 ;
wire \out_link[6] ;
wire \i_rtl_1|adder[0]|unreg_res_node[6]~118 ;
wire \i_rtl_1|adder[0]|ps[6]~57sexp ;
wire \i_rtl_1|adder[0]|unreg_res_node[6]~119 ;
wire \add_num[6] ;
wire \i_rtl_1|adder[0]|tot_cin_node[6]~11 ;
wire \add_num[7] ;
wire \i_rtl_1|adder[0]|prop_node[3]~77 ;
wire \i_rtl_1|adder[0]|bg_out~40 ;
wire \i_rtl_1|adder[0]|bg_out~39 ;
wire \i_rtl_1|look_ahead_unit|$00004~4 ;
wire \out_link[8] ;
wire \add_num[8] ;
wire \i_rtl_1|look_ahead_unit|$00005~389 ;
wire \i_rtl_1|look_ahead_unit|$00005~390 ;
wire \out_link[9] ;
wire \i_rtl_1|adder[1]|unreg_res_node[1]~60 ;
wire \i_rtl_1|adder[1]|unreg_res_node[1]~61 ;
wire \add_num[9] ;
wire \i_rtl_1|look_ahead_unit|$00005~388 ;
wire \out_link[10] ;
wire \i_rtl_1|adder[1]|tot_cin_node[1]~94 ;
wire \add_num[10] ;
wire \i_rtl_1|look_ahead_unit|$00005~387 ;
wire \i_rtl_1|adder[1]|pc[2]~73 ;
wire \i_rtl_1|adder[1]|gc[2]~66 ;
wire \out_link[11] ;
wire \add_num[11] ;
wire \i_rtl_1|look_ahead_unit|$00005~386 ;
wire \i_rtl_1|adder[1]|tot_cin_node[6]~95 ;
wire \i_rtl_1|adder[1]|tot_cin_node[6]~85 ;
wire \out_link[12] ;
wire \add_num[12] ;
wire \i77~15 ;
wire \out_link[13] ;
wire \i_rtl_1|adder[1]|ps[4]~63sexp ;
wire \add_num[13] ;
wire \out_link[14] ;
wire \i_rtl_1|look_ahead_unit|$00005~385 ;
wire \i76~18 ;
wire \i76~11 ;
wire \i76~10 ;
wire \i76~8 ;
wire \add_num[14] ;
wire \i_rtl_1|adder[1]|unreg_res_node[7]~46 ;
wire \out_link[15] ;
wire \i_rtl_1|adder[1]|unreg_res_node[7]~48 ;
wire \i_rtl_1|adder[1]|unreg_res_node[7]~49 ;
wire \i_rtl_1|adder[1]|unreg_res_node[7]~50 ;
wire \add_num[15] ;
wire \i_rtl_1|adder[1]|genr_node[3]~91 ;
wire \i_rtl_1|adder[1]|prop_node[3]~100 ;
wire \i_rtl_1|adder[1]|prop_node[2]~105 ;
wire \i_rtl_1|look_ahead_unit|$00005~403 ;