📄 ryxiangwei.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:d:\modeltech_5.7g\examples\ryxiangwei\ryxiangwei.rpt
ryxiangwei
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
36 - - - 07 OUTPUT 0 1 0 0 gate0
8 - - - 03 OUTPUT 0 1 0 0 gate1
37 - - - 09 OUTPUT 0 1 0 0 gate2
28 - - C -- OUTPUT 0 1 0 0 gate3
29 - - C -- OUTPUT 0 1 0 0 gate4
69 - - A -- OUTPUT 0 1 0 0 gate5
60 - - C -- OUTPUT 0 1 0 0 gate6
30 - - C -- OUTPUT 0 1 0 0 gate7
59 - - C -- OUTPUT 0 1 0 0 gate8
27 - - C -- OUTPUT 0 1 0 0 out_addr0
10 - - - 01 OUTPUT 0 1 0 0 out_addr1
81 - - - 22 OUTPUT 0 1 0 0 out_addr2
71 - - A -- OUTPUT 0 1 0 0 out_addr3
54 - - - 21 OUTPUT 0 1 0 0 out_addr4
58 - - C -- OUTPUT 0 1 0 0 out_addr5
50 - - - 17 OUTPUT 0 1 0 0 out_addr6
61 - - C -- OUTPUT 0 1 0 0 out_addr7
62 - - C -- OUTPUT 0 1 0 0 out_addr8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\modeltech_5.7g\examples\ryxiangwei\ryxiangwei.rpt
ryxiangwei
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 13 SOFT s ! 1 0 0 25 Load~1
- 6 - C 12 OR2 0 4 0 2 |lpm_add_sub:652|addcore:adder|pcarry1
- 8 - C 12 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry2
- 3 - C 14 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry3
- 6 - C 14 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry4
- 8 - C 14 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry5
- 4 - C 15 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry6
- 7 - C 15 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry7
- 1 - C 15 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry8
- 6 - B 23 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry9
- 4 - B 23 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry10
- 6 - B 18 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry11
- 1 - B 18 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry12
- 7 - B 14 OR2 0 3 0 2 |lpm_add_sub:652|addcore:adder|pcarry13
- 4 - B 14 OR2 0 3 0 3 |lpm_add_sub:652|addcore:adder|pcarry14
- 1 - C 12 AND2 0 2 0 1 |lpm_add_sub:652|addcore:adder|:132
- 4 - C 04 OR2 0 4 0 4 |lpm_add_sub:652|addcore:adder|:199
- 7 - C 03 AND2 0 4 0 5 |lpm_add_sub:652|addcore:adder|:211
- 4 - C 20 AND2 0 3 0 5 |lpm_add_sub:652|addcore:adder|:219
- 1 - C 04 OR2 0 4 0 6 |lpm_add_sub:652|addcore:adder|:250
- 2 - C 03 OR2 0 2 0 5 |lpm_add_sub:652|addcore:adder|:251
- 5 - C 03 OR2 0 3 0 6 |lpm_add_sub:652|addcore:adder|:252
- 6 - C 03 OR2 0 4 0 6 |lpm_add_sub:652|addcore:adder|:253
- 7 - C 20 OR2 0 2 0 5 |lpm_add_sub:652|addcore:adder|:254
- 2 - C 20 OR2 0 3 0 7 |lpm_add_sub:652|addcore:adder|:255
- 6 - C 24 OR2 0 2 0 5 |lpm_add_sub:652|addcore:adder|:256
- 2 - C 24 OR2 0 3 0 7 |lpm_add_sub:652|addcore:adder|:257
- 1 - C 24 OR2 0 4 0 6 |lpm_add_sub:652|addcore:adder|:258
- 3 - C 01 OR2 0 4 0 3 |lpm_add_sub:653|addcore:adder|pcarry1
- 8 - C 16 OR2 0 3 0 3 |lpm_add_sub:653|addcore:adder|pcarry2
- 6 - C 16 OR2 0 3 0 2 |lpm_add_sub:653|addcore:adder|pcarry3
- 1 - C 18 OR2 0 3 0 2 |lpm_add_sub:653|addcore:adder|pcarry4
- 3 - C 18 OR2 0 3 0 2 |lpm_add_sub:653|addcore:adder|pcarry5
- 5 - C 18 OR2 0 3 0 2 |lpm_add_sub:653|addcore:adder|pcarry6
- 8 - C 18 OR2 0 3 0 1 |lpm_add_sub:653|addcore:adder|pcarry7
- 7 - C 16 OR2 0 3 0 3 |lpm_add_sub:653|addcore:adder|:117
- 7 - C 01 OR2 s 0 3 0 1 |lpm_add_sub:654|addcore:adder|~115~1
- 3 - C 16 OR2 0 4 0 4 |lpm_add_sub:655|addcore:adder|pcarry3
- 4 - C 17 OR2 0 4 0 2 |lpm_add_sub:655|addcore:adder|pcarry6
- 7 - C 17 AND2 0 2 0 1 |lpm_add_sub:655|addcore:adder|:91
- 7 - C 22 OR2 s 0 3 0 1 |lpm_add_sub:655|addcore:adder|~122~1
- 5 - C 16 OR2 0 3 0 2 |lpm_add_sub:656|addcore:adder|pcarry3
- 8 - C 20 OR2 0 4 0 2 |lpm_add_sub:656|addcore:adder|pcarry4
- 3 - C 17 OR2 0 3 0 2 |lpm_add_sub:656|addcore:adder|pcarry5
- 1 - C 17 OR2 0 4 0 2 |lpm_add_sub:656|addcore:adder|pcarry6
- 5 - C 22 OR2 0 3 0 2 |lpm_add_sub:656|addcore:adder|pcarry7
- 1 - C 16 OR2 0 3 0 2 |lpm_add_sub:656|addcore:adder|:116
- 3 - C 20 OR2 0 4 0 4 |lpm_add_sub:656|addcore:adder|:118
- 2 - C 17 OR2 0 3 0 3 |lpm_add_sub:656|addcore:adder|:119
- 5 - C 17 OR2 0 4 0 2 |lpm_add_sub:656|addcore:adder|:120
- 3 - C 22 OR2 0 3 0 2 |lpm_add_sub:656|addcore:adder|:121
- 2 - C 04 OR2 s 0 3 0 1 ~59~1
- 3 - C 04 OR2 s 0 4 0 1 ~59~2
- 7 - C 04 OR2 ! 0 4 0 4 :59
- 1 - A 23 DFFE + 0 1 0 25 out_link_link16 (:87)
- 2 - B 14 DFFE + 0 1 0 2 out_link_link15 (:88)
- 5 - B 14 DFFE + 0 1 0 2 out_link_link14 (:89)
- 2 - B 18 DFFE + 0 1 0 2 out_link_link13 (:90)
- 8 - B 18 DFFE + 0 1 0 2 out_link_link12 (:91)
- 1 - B 23 DFFE + 0 1 0 2 out_link_link11 (:92)
- 8 - B 23 DFFE + 0 1 0 2 out_link_link10 (:93)
- 1 - C 23 DFFE + 0 1 0 2 out_link_link9 (:94)
- 5 - C 23 DFFE + 0 1 0 3 out_link_link8 (:95)
- 8 - C 23 DFFE + 0 1 0 3 out_link_link7 (:96)
- 2 - C 23 DFFE + 0 1 0 3 out_link_link6 (:97)
- 5 - C 19 DFFE + 0 1 0 3 out_link_link5 (:98)
- 1 - C 19 DFFE + 0 1 0 3 out_link_link4 (:99)
- 7 - C 19 DFFE + 0 1 0 3 out_link_link3 (:100)
- 6 - C 19 DFFE + 0 1 0 3 out_link_link2 (:101)
- 2 - C 01 DFFE + 0 1 0 3 out_link_link1 (:102)
- 1 - C 06 DFFE + 1 0 0 3 out_link_link0 (:103)
- 6 - C 04 DFFE + 0 3 0 3 out_link15 (:157)
- 6 - B 14 DFFE + 0 3 0 2 out_link14 (:158)
- 1 - B 14 DFFE + 0 3 0 2 out_link13 (:159)
- 5 - B 18 DFFE + 0 3 0 2 out_link12 (:160)
- 3 - B 18 DFFE + 0 3 0 2 out_link11 (:161)
- 5 - B 23 DFFE + 0 3 0 2 out_link10 (:162)
- 2 - B 23 DFFE + 0 3 0 2 out_link9 (:163)
- 6 - C 15 DFFE + 0 3 0 2 out_link8 (:164)
- 3 - C 15 DFFE + 0 3 0 2 out_link7 (:165)
- 7 - C 23 DFFE + 0 3 0 2 out_link6 (:166)
- 5 - C 14 DFFE + 0 3 0 2 out_link5 (:167)
- 3 - C 19 DFFE + 0 3 0 2 out_link4 (:168)
- 1 - C 14 DFFE + 0 3 0 2 out_link3 (:169)
- 5 - C 12 DFFE + 0 3 0 2 out_link2 (:170)
- 8 - C 01 DFFE + 0 3 0 2 out_link1 (:171)
- 4 - C 12 DFFE + 0 3 0 3 out_link0 (:172)
- 5 - C 24 DFFE + 1 2 0 1 add_num24 (:365)
- 3 - C 24 DFFE + 1 1 0 2 add_num23 (:366)
- 7 - C 24 DFFE + 1 2 0 5 add_num22 (:367)
- 6 - C 20 DFFE + 1 2 0 2 add_num21 (:368)
- 5 - C 20 DFFE + 1 1 0 5 add_num20 (:369)
- 4 - C 03 DFFE + 1 2 0 2 add_num19 (:370)
- 3 - C 03 DFFE + 1 1 0 3 add_num18 (:371)
- 8 - C 03 DFFE + 1 1 0 4 add_num17 (:372)
- 8 - C 04 DFFE + 1 1 0 2 add_num16 (:373)
- 5 - C 04 DFFE + 1 2 0 2 add_num15 (:374)
- 8 - B 14 DFFE + 1 2 0 1 add_num14 (:375)
- 3 - B 14 DFFE + 1 2 0 1 add_num13 (:376)
- 7 - B 18 DFFE + 1 2 0 1 add_num12 (:377)
- 4 - B 18 DFFE + 1 2 0 1 add_num11 (:378)
- 7 - B 23 DFFE + 1 2 0 1 add_num10 (:379)
- 3 - B 23 DFFE + 1 2 0 1 add_num9 (:380)
- 8 - C 15 DFFE + 1 2 0 1 add_num8 (:381)
- 5 - C 15 DFFE + 1 2 0 1 add_num7 (:382)
- 2 - C 15 DFFE + 1 2 0 1 add_num6 (:383)
- 7 - C 14 DFFE + 1 2 0 1 add_num5 (:384)
- 4 - C 14 DFFE + 1 2 0 1 add_num4 (:385)
- 2 - C 14 DFFE + 1 2 0 1 add_num3 (:386)
- 7 - C 12 DFFE + 1 2 0 1 add_num2 (:387)
- 2 - C 12 DFFE + 1 2 0 1 add_num1 (:388)
- 3 - C 12 DFFE + 1 1 0 2 add_num0 (:389)
- 3 - C 23 DFFE + 0 3 0 3 out_link_link18 (:456)
- 4 - C 23 DFFE + 0 3 0 4 out_link_link17 (:457)
- 6 - C 23 DFFE + 0 3 0 4 :458
- 4 - C 19 DFFE + 0 3 0 4 :459
- 2 - C 19 DFFE + 0 3 0 4 :460
- 2 - C 16 DFFE + 0 3 0 3 :461
- 4 - C 16 DFFE + 0 3 0 3 :462
- 4 - C 01 DFFE + 0 3 0 2 :463
- 5 - C 01 DFFE + 0 3 0 3 :464
- 7 - C 18 OR2 ! 0 4 0 8 :476
- 6 - C 18 OR2 ! 0 4 0 1 :481
- 2 - C 18 OR2 s 0 4 0 1 ~489~1
- 4 - C 18 OR2 ! 0 4 0 1 :489
- 1 - C 20 OR2 ! 0 4 0 1 :496
- 8 - C 22 OR2 0 4 0 1 :532
- 6 - C 22 OR2 0 4 0 1 :560
- 4 - C 22 OR2 0 3 0 1 :570
- 8 - C 17 OR2 0 4 0 1 :571
- 6 - C 21 OR2 0 4 0 1 :572
- 3 - C 21 OR2 0 3 0 1 :573
- 1 - C 21 OR2 0 3 0 1 :574
- 1 - C 22 DFFE + 1 2 1 0 :606
- 2 - C 22 DFFE + 1 1 1 0 :607
- 6 - C 17 DFFE + 1 1 1 0 :608
- 7 - C 21 DFFE + 1 1 1 0 :609
- 5 - C 21 DFFE + 1 1 1 0 :610
- 4 - C 21 DFFE + 1 1 1 0 :611
- 2 - C 21 DFFE + 1 2 1 0 :612
- 6 - C 01 DFFE + 1 2 1 0 :613
- 1 - C 01 DFFE + 1 2 1 0 :614
- 8 - C 24 DFFE + 1 1 1 0 :643
- 7 - C 09 DFFE + 1 1 1 0 :644
- 4 - C 24 DFFE + 1 1 1 0 :645
- 8 - C 13 DFFE + 1 1 1 0 :646
- 8 - C 02 DFFE + 1 1 1 0 :647
- 3 - C 07 DFFE + 1 1 1 0 :648
- 4 - C 10 DFFE + 1 1 1 0 :649
- 1 - C 03 DFFE + 1 1 1 0 :650
- 1 - C 08 DFFE + 1 1 1 0 :651
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:d:\modeltech_5.7g\examples\ryxiangwei\ryxiangwei.rpt
ryxiangwei
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 25/ 96( 26%) 11/ 48( 22%) 31/ 48( 64%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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